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Action:
if (PC.em != supervisor)
generate_fault(TYPE.MISMATCH);
switch (src1[7:0]) {
case 0:
case 1:
case 2:
case 3:
case 4:
INSTRUCTION SET REFERENCE
# Disable instruction cache.
disable_instruction_cache( );
break;
# Enable instruction cache.
enable_instruction_cache( );
break;
# Globally invalidate instruction cache.
# Includes locked lines also.
invalidate_instruction_cache( );
unlock_icache( );
break;
# Load & Lock code into Instruction-Cache
# src_dst has number of contiguous blocks to lock.
# src2 has starting address of code to lock.
# On the i960 Jx, src2 is aligned to a quad word boundary
aligned_addr = src2 & 0xFFFFFFF0;
invalidate(I-cache); unlock(I-cache);
for (j = 0; j < src_dst; j++)
{
way = way_associated_with_block(j);
start = src2 + j*block_size;
end = start + block_size;
for (i = start; i < end; i=i+4)
{ set = set_associated_with(i);
word = word_associated_with(i);
Icache_line[set][way][word] =
update_tag_n_valid_bits(set,way,word)
lock_icache(set,way,word);
} } break;
# Get instruction cache status into src_dst.
if (Icache_enabled) src_dst[0] = 1;
else src_dst[0] = 0;
# Atom is 4 bytes.
src_dst[7:4] = log2(bytes per atom);
# 4 atoms per line.
src_dst[11:8] = log2(atoms per line);
src_dst[15:12] = log2(number of sets);
src_dst[27:16] = number of ways-1; #in lines per set
# cache size = ([27:16]+1) << ([7:4] + [11:8] + [15:12])
break;
6
memory[i];
6-63
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