Table of Contents
Advertisement
INITIALIZATION AND SYSTEM REQUIREMENTS
At initialization, the processor loads the Supervisor Stack Pointer (SSP) from the system procedure
table, aligns it to a 16-byte boundary, and caches the pointer in the SSP memory-mapped control
register (see
section 3.3, "MEMORY-MAPPED CONTROL REGISTERS" (pg.
3-6)). The
supervisor stack pointer is located in the preamble of the system procedure table at byte offset 12
from the base address. The system procedure table base address is programmed in the PRCB. See
section 7.5.1, "System Procedure Table" (pg. 7-15)
for the format of the system procedure table.
At initialization, the NMI vector is loaded from the interrupt table and saved at location
0000 0000H of the internal data RAM. The interrupt table is typically programmed in the boot
ROM and then relocated to internal RAM by reinitializing the processor.
The fault table is typically located in boot ROM. If it is necessary to locate the fault table in RAM,
the processor must be reinitialized.
The remaining data structures that an application may need are the user stack, supervisor stack and
interrupt stack. These stacks must be located in a system's RAM.
At initialization, the processor loads the interrupt stack pointer in the ISP memory-mapped
register. It then zeroes-out the low order four bits of the ISP, to align it to a 16 byte boundary, and
places it in the FP. To ensure correct operation, the value needed for ISP from the PRCB must be
quad-word aligned.
12
12-11
Advertisement
Table of Contents
