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EXTERNAL BUS
The processor's bus control unit is designed to decouple bus activity from instruction execution in
the core as much as possible. When a load or store instruction or instruction prefetch is issued, a
bus request is generated in the bus control unit. The bus control unit independently processes the
request and retrieves data from memory for load instructions and instruction prefetches. The bus
control unit delivers data to memory for store instructions.
The i960 architecture defines byte, short word, word, double word, triple word and quad word data
lengths for load and store instructions. When a load or store instruction is encountered, the
processor issues a bus request of the appropriate data length: for example,
requests that four
ldq
words of data be retrieved from memory;
requests that a single byte be delivered to memory.
stob
The processor always fetches instructions using double or quad word bus requests.
A bus access is defined as a bus transaction bounded by the assertion of ADS (address/data status)
and de-assertion of BLAST (burst last) signals, which are outputs from the processor. A bus
access consists of one to four data transfers. During each transfer, the processor either reads data
or drives data on the bus. The number of transfers per access and the number of accesses per
request is governed by the requested data length, the programmed width of the bus and the
alignment of the address.
14.2.1
Basic Bus States
The bus has five basic bus states: idle (Ti), address (Ta), wait/data (Tw/Td), recovery (Tr), and hold
(Th). During system operation, the processor continuously enters and exits different bus states.
The bus occupies the idle (Ti) state when no address/data transactions are in progress and when
RESET is asserted. When the processor needs to initiate a bus access, it enters the Ta state to
transmit the address.
Following a Ta state, the bus enters the Tw/Td state to transmit or receive data on the address/data
lines. Assertion of the RDYRCV input signal indicates completion of each transfer. When data is
not ready, the processor can wait as long as necessary for the memory or I/O device to respond.
After the data transfer, the bus exits the Tw/Td state and enters the recovery (Tr) state. In the case
of a burst transaction, the bus exits the Td state and re-enters the Td/Tw state to transfer the next
data word. The processor asserts the BLAST signal during the last Tw/Td states of an access.
Once all data words transfer in a burst access (up to four), the bus enters the Tr state to allow
devices on the bus to recover.
The processor remains in the Tr state until RDYRCV is deasserted. When the recovery state
completes, the bus enters the Ti state if no new accesses are required. If an access is pending, the
bus enters the Ta state to transmit the new address.
14-2
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