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3.7.3
Process Controls (PC) Register
The PC register
(Figure
3-4) is used to control processor activity and show the processor's current
state. The PC register execution mode flag (bit 1) indicates that the processor is operating in either
user mode (0) or supervisor mode (1). The processor automatically sets this flag on a system call
when a switch from user mode to supervisor mode occurs and it clears the flag on a return from
supervisor mode. (User and supervisor modes are described in
PROTECTION MODEL" (pg.
Trace-Enable Bit - PC.te
(0) Globally disable trace faults
(1) Globally enable trace faults
Execution-Mode Flag - PC.em
(0) user mode
(1) supervisor mode
Trace-Fault-Pending - PC.tfp
(0) no fault pending
(1) fault pending
State Flag - PC.s
(0) executing
(1) interrupted
Priority Field - PC.p
(0-31) process priority
31
28
24
Reserved
(Do not modify)
Figure 3-4. Process Controls (PC) Register
PC register state flag (bit 13) indicates the processor state: executing (0) or interrupted (1). When the
processor is servicing an interrupt, its state is interrupted. Otherwise, the processor's state is executing.
While in the interrupted state, the processor can receive and handle additional interrupts. When
nested interrupts occur, the processor remains in the interrupted state until all interrupts are
handled, then switches back to the executing state on the return from the initial interrupt procedure.
The PC register priority field (bits 16 through 20) indicates the processor's current executing or
interrupted priority. The architecture defines a mechanism for prioritizing execution of code,
servicing interrupts and servicing other implementation-dependent tasks or events. This
mechanism defines 32 priority levels, ranging from 0 (the lowest priority level) to 31 (the highest).
The priority field always reflects the current priority of the processor. Software can change this
priority by use of the
modpc
3-23).
p
p
p
p p
s
4
3
2
1 0
20
16
instruction.
PROGRAMMING ENVIRONMENT
section 3.8, "USER-SUPERVISOR
t
f
p
12
8
4
3
e
t
m e
0
3-21
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