Table of Contents
Advertisement
INITIALIZATION AND SYSTEM REQUIREMENTS
12.6
SYSTEM REQUIREMENTS
The following sections discuss generic hardware requirements for a system built around the i960
Jx processor. This section describes electrical characteristics of the processor's interface to the
external circuit. The CLKIN, RESET, STEST, FAIL, ONCE, V
detail. Specific signal functions for the external bus signals and interrupt inputs are discussed in
their respective sections in this manual.
12.6.1
Input Clock (CLKIN)
The clock input (CLKIN) determines processor execution rate and timing. It is designed to be
driven by most common TTL crystal clock oscillators. The clock input must be free of noise and
conform with the specifications listed in the data sheet. CLKIN input capacitance is minimal; for
this reason, it may be necessary to terminate the CLKIN circuit board trace at the processor to
reduce overshoot and undershoot.
12.6.2
Power and Ground Requirements (V
The large number of V
and V
SS
connections to the chip and reduces transient noise induced by current surges. The i960 Jx
processor is implemented in CHMOS IV technology. Unlike NMOS processes, power dissipation
in the CHMOS process is due to capacitive charging and discharging on-chip and in the
processor's output buffers; there is almost no DC power component. The nature of this power
consumption results in current surges when capacitors charge and discharge. The processor's
power consumption depends mostly on frequency. It also depends on voltage and capacitive bus
load (see appropriate data sheet listed below).
To reduce clock skew on the i960 Jx processor, the V
circuit is isolated on the pinout. A lowpass filter reduces noise induced clock jitter and its effects
on timing relationships in system designs. Refer to
These documents contain specific circuit examples for the V
12-34
, V
C C
pins effectively reduces the impedance of power and ground
CC
CCPLL
section 1.4, "Related Documents" (pg.
and V
pins are described in
SS
CC
)
S S
pin for the Phase Lock Loop (PLL)
pin.
CCPLL
1-10).
Advertisement
Table of Contents
