Intel Quark SoC X1000 Processor Manuals

Manuals and User Guides for Intel Quark SoC X1000 Processor. We have 5 Intel Quark SoC X1000 Processor manuals available for free PDF download: Developer's Manual, Design Manual, Software User's Manual, User Manual

Intel Quark SoC X1000 Developer's Manual (311 pages)

Brand: Intel | Category: Motherboard | Size: 2 MB

Revision History
3
Table of Contents
4
About this Manual
17
- Manual Contents
  17
- Notation Conventions
  18
- Special Terminology
  19
- Related Documents
  20
Intel Quark Soc X1000 Core Overview
21
Architectural Overview
22
- Internal Architecture
  22
- System Architecture
  22
- Memory Organization
  22
  - Address Spaces
    23
  - Segment Register Usage
    24
- Address Translation
  24
- I/O Space
  25
- Addressing Modes
  25
  - Addressing Modes Overview
    25
Segment Register Selection Rules
25
BASE and INDEX Registers for 16- and 32-Bit Addresses
28
- Unsigned Data Types
  29
- Signed Data Types
  29
- Data Types
  29
  - BCD Data Types
    30
  - Floating-Point Data Types
    30
  - String Data Types
    30
  - ASCII Data Types
    31
- Data Types
  31
  - Pointer Data Types
    32
- String and ASCII Data Types
  32
  - Little Endian Vs. Big Endian Data Formats
    33
- Interrupts
  33
  - Interrupts and Exceptions
    33
- Big Vs. Little Endian Memory Format
  33
  - Interrupt Processing
    34
  - Maskable Interrupt
    34
  - Non-Maskable Interrupt
    35
Interrupt Vector Assignments
35
FPU Interrupt Vector Assignments
35
- Software Interrupts
  36
- Interrupt and Exception Priorities
  36
- Instruction Restart
  37
Sequence of Exception Checking
37
- Double Fault
  38
- Floating-Point Interrupt Vectors
  38
Interrupt Vectors Used by FPU
38
System Register Organization
39
- Register Set Overview
  39
- Floating-Point Registers
  39
- Base Architecture Registers
  39
  - General Purpose Registers
    40
Base Architecture Registers
40
- Instruction Pointer
  41
- Flags Register
  41
Flag Registers
41
Data Type Alignment Requirements
42
- Segment Registers
  44
- Segment Descriptor Cache Registers
  44
- System-Level Registers
  45
  - Control Registers
    46
System-Level Registers
46
- Control Register 0 (CR0)
  47
Control Registers
47
On-Chip Cache Control Modes
47
Intel ® Quark Soc X1000 Core Operating Modes
48
Recommended Values of the Floating-Point Related Bits for Intel
50
Interpreting Different Combinations of EM, TS and MP Bits
50
- Control Register 1 (CR1)
  51
- Control Register 2 (CR2)
  51
- Control Register 3 (CR3)
  51
- Control Register 4 (CR4)
  51
- System Address Registers
  52
- Floating-Point Registers
  53
Floating-Point Status Word
55
Condition Code Interpretation after FPREM and FPREM1 Instructions
56
Floating-Point Condition Code Interpretation
56
Condition Code Resulting from Comparison
57
Condition Code Defining Operand Class
57
- Instruction and Data Pointers
  58
FPU Exceptions
58
Protected Mode FPU Instructions and Data Pointer Image in Memory (32-Bit Format)
59
Real Mode FPU Instruction and Data Pointer Image in Memory (32-Bit Format)
59
Protected Mode FPU Instruction and Data Pointer Image in Memory (16-Bit Format)
60
Real Mode FPU Instruction and Data Pointer Image in Memory (16-Bit Format)
60
- FPU Control Word
  61
- Debug and Test Registers
  62
  - Debug Registers
    62
  - Test Registers
    62
- Register Accessibility
  62
  - FPU Register Usage
    63
- Reserved Bits and Software Compatibility
  63
Register Usage
63
FPU Register Usage Differences
63
- Intel ® Quark Core Model Specific Registers (Msrs)
  64
Real Mode Architecture
65
- Introduction
  65
Instruction Forms in Which LOCK Prefix Is Legal
65
- Memory Addressing
  66
- Reserved Locations
  66
Real Address Mode Addressing
66
- Interrupts
  67
- Shutdown and Halt
  67
Exceptions with Different Meanings in Real Mode
67
Protected Mode Architecture
68
- Addressing Mechanism
  68
- Segmentation
  69
  - Segmentation Introduction
    69
Protected Mode Addressing
69
Paging and Segmentation
69
- Terminology
  70
- Descriptor Tables
  70
  - Descriptor Tables Introduction
    70
  - Global Descriptor Table
    71
  - Local Descriptor Table
    71
  - Interrupt Descriptor Table
    71
Descriptor Table Registers
71
- Descriptors
  72
  - Descriptor Attribute Bits
    72
  - Intel ® Quark Core Code, Data Descriptors (S=1)
    72
Interrupt Descriptor Table Register Use
72
Segment Descriptors
73
- System Descriptor Formats
  74
Access Rights Byte Definition for Code and Data Descriptions
74
System Segment Descriptors
75
Gate Descriptor Formats
76
Example Descriptor Selection
78
Segment Descriptor Caches for Real Address Mode
79
Segment Descriptor Caches for Protected Mode (Loaded Per Descriptor)
80
- Protection
  81
  - Protection Concepts
    81
Segment Descriptor Caches for Virtual 8086 Mode Within Protected Mode
81
- Rules of Privilege
  82
- Privilege Levels
  82
  - Task Privilege
    82
  - Selector Privilege (RPL)
    82
Four-Level Hierarchical Protection
82
- I/O Privilege and I/O Permission Bitmap
  83
Intel ® Quark Core TSS and TSS Registers
84
- Privilege Validation
  85
- Descriptor Access
  85
Sample I/O Permission Bit Map
85
Pointer Test Instructions
85
- Privilege Level Transfers
  86
Descriptor Types Used for Control Transfer
86
- Call Gates
  87
- Task Switching
  88
Intel ® Quark Core TSS
88
- Floating-Point Task Switching
  89
- Initialization and Transition to Protected Mode
  89
Simple Protected System
90
- Paging
  91
  - Paging Concepts
    91
  - Paging Organization
    91
    
    Page Mechanism
    91
    
    Page Descriptor Base Register
    91
GDT Descriptors for Simple System
91
- Page Directory
  92
- Page Tables
  92
- Page Directory/Table Entries
  92
- Paging-Mode Modifiers
  92
- PAE Paging
  93
  - PDPTE Registers
    93
Use of CR3 with PAE Paging
93
- Linear-Address Translation with PAE Paging
  94
Format of a PAE Page-Directory-Pointer-Table Entry (PDPTE)
94
Linear-Address Translation to a 4-Kbyte Page Using PAE Paging
95
Format of a PAE Page-Directory Entry that Maps a 2-Mbyte Page
96
Linear-Address Translation to a 2-Mbyte Page Using PAE Paging
96
Format of a PAE Page-Directory Entry that References a
97
Format of a PAE Page-Table Entry that Maps a 4-Kbyte Page
97
Formats of CR3 and Paging-Structure Entries in 32-Bit Mode with PAE Paging Disabled
98
Formats of CR3 and Paging-Structure Entries in 32-Bit Mode with PAE Paging Enabled
99
- Access Rights
  100
Page Level Protection Attributes
103
- Page-Fault Exceptions
  104
Page Cacheability
103
Translation Lookaside Buffer
104
Page-Fault Error Code
105
- Paging Operation
  106
- Operating System Responsibilities
  107
- Virtual 8086 Environment
  107
  - Executing Programs
    107
Page Fault System Information
107
- Virtual 8086 Mode Addressing Mechanism
  108
- Paging in Virtual Mode
  108
Virtual 8086 Environment Memory Management
108
Virtual 8086 Environment Interrupt and Call Handling
111
- Task Switches to and from Virtual 8086 Mode
  112
- Transitions through Trap and Interrupt Gates, and IRET
  112
On-Chip Cache
114
- Cache Organization
  114
On-Chip Cache Physical Organization
114
- Write-Back Enhanced Intel ® Quark Soc X1000 Core Cache
  115
- Quark Soc X1000
  115
Write-Back Enhanced Intel ® Quark Soc X1000 Core WB/WT# Initialization
115
- Cache Control
  116
  - Write-Back Enhanced Intel Operating Modes
    116
Cache Operating Modes
116
- Cache Line Fills
  117
- Cache Line Invalidations
  118
  - Write-Back Enhanced Intel
    118
    
    Write-Back Mode Invalidation
    118
- Cache Replacement
  118
Write-Back Enhanced Intel Cycle
118
- Page Cacheability
  119
  - Cacheability
    119
Quark Soc X1000
118
Encoding of the Special Cycles for Write-Back Cache
119
On-Chip Cache Replacement Strategy
119
- Page Cacheability
  121
- Cache Flushing
  122
Cache State Transitions for Write-Back Enhanced Intel Core-Initiated Unlocked Read Cycles
124
- Detecting On-Chip Write-Back Cache of the Write-Back Enhanced Intel Quark Soc X1000 Core
  125
Cache State Transitions for Write-Back Enhanced Intel Core-Initiated Write Cycles
125
Cache State Transitions During Snoop Cycles
125
Quark Soc X1000
125
System Management Mode (SMM) Architectures
127
- SMM Overview
  127
- Terminology
  127
- System Management Interrupt Processing
  128
Basic SMI# Interrupt Service
128
- System Management Interrupt (SMI#)
  129
- SMI# Active (SMIACT#)
  129
Basic SMI# Hardware Interface
129
- Smram
  130
SMI# Timing for Servicing an I/O Trap
130
- SMRAM State Save Map
  131
Redirecting System Memory Addresses to SMRAM
132
- Exit from SMM
  133
- System Management Mode Programming Model
  134
  - Entering System Management Mode
    134
  - Processor Environment
    135
Transition to and from System Management Mode
135
- Write-Back Enhanced Intel ® Quark Soc X1000 Core Environment
  136
- Executing System Management Mode Handler
  136
SMM Initial Processor Core Register Settings
136
- Exceptions and Interrupts Within System Management Mode
  137
- SMM Features
  138
  - SMM Revision Identifier
    138
  - Auto Halt Restart
    138
Bit Values for SMM Revision Identifier
138
- I/O Instruction Restart
  139
Bit Values for Auto HALT Restart
139
- SMM Base Relocation
  140
Auto HALT Restart
139
SMM Base Location
140
I/O Instruction Restart Value
140
- SMM System Design Considerations
  141
  - SMRAM Interface
    141
SMRAM Usage
141
- Cache Flushes
  142
SMRAM Location
142
FLUSH# Mechanism During SMM
143
Cached SMM
143
- Write-Back Enhanced Intel Management Mode and Cache Flushing
  144
Non-Cached SMM
144
Cache Flushing (Non-Overlaid SMRAM)
144
Cache Flushing (Overlaid SMRAM)
145
- Snoop During SMM
  146
- A20M# Pin and SMBASE Relocation
  146
- Processor Reset During SMM
  146
- SMM and Second-Level Write Buffers
  147
- Nested Smi#S and I/O Restart
  147
- SMM Software Considerations
  147
  - SMM Code Considerations
    147
  - Exception Handling
    148
  - Halt During SMM
    148
  - Relocating SMRAM to an Address above One Megabyte
    148
Hardware Interface
149
- Introduction
  149
- Signal Descriptions
  150
  - Clock (CLK)
    150
  - Address Bus (A[31:2], BE[3:0]#)
    150
Functional Signal Groupings
150
- Data Lines (D[31:0])
  151
- Parity
  151
  - Data Parity Input/Outputs (DP[3:0])
    151
  - Parity Status Output (PCHK#)
    151
  - Bus Cycle Definition
    152
    
    M/IO#, D/C#, W/R# Outputs
    152
    
    Bus Lock Output (LOCK#)
    152
ADS# Initiated Bus Cycle Definitions
152
- Pseudo-Lock Output (PLOCK#)
  153
- PLOCK# Floating-Point Considerations
  153
- Bus Control
  153
  - Address Status Output (ADS#)
    153
  - Non-Burst Ready Input (RDY#)
    153
  - Burst Control
    154
    
    Burst Ready Input (BRDY#)
    154
    
    Burst Last Output (BLAST#)
    154
  - Interrupt Signals
    154
  - Reset Input (RESET)
    154
  - Soft Reset Input (SRESET)
    155
  - System Management Interrupt Request Input (SMI#)
    155
  - System Management Mode Active Output (SMIACT#)
    155
  - Maskable Interrupt Request Input (INTR)
    155
  - Non-Maskable Interrupt Request Input (NMI)
    156
  - Stop Clock Interrupt Request Input (STPCLK#)
    156
- Bus Arbitration Signals
  156
  - Bus Request Output (BREQ)
    156
  - Bus Hold Request Input (HOLD)
    156
  - Bus Hold Acknowledge Output (HLDA)
    157
  - Backoff Input (BOFF#)
    157
- Cache Invalidation
  157
  - Address Hold Request Input (AHOLD)
    158
  - External Address Valid Input (EADS#)
    158
- Cache Control
  158
  - Cache Enable Input (KEN#)
    158
  - Cache Flush Input (FLUSH#)
    158
- Page Cacheability (PWT, PCD)
  159
- Reserved
  159
- Numeric Error Reporting (FERR#, IGNNE#)
  159
  - Floating-Point Error Output (FERR#)
    159
  - Ignore Numeric Error Input (IGNNE#)
    160
- Bus Size Control (BS16#, BS8#)
  160
- Address Bit 20 Mask (A20M#)
  161
  - Enhanced Bus Features
    161
  - Cacheability (CACHE#)
    161
Differences between CACHE# and PCD
161
- Cache Flush (FLUSH#)
  162
- Hit/Miss to a Modified Line (HITM#)
  162
CACHE# Vs. Other Intel Quark Core Signals
162
- Soft Reset (SRESET)
  163
- Invalidation Request (INV)
  163
HITM# Vs. Other Intel
163
INV Vs. Other Intel ® Quark Core Signals
163
- Write-Back/Write-Through (WB/WT#)
  164
- Pseudo-Lock Output (PLOCK#)
  164
- Test Signals
  164
  - Test Clock (TCK)
    164
WB/WT# Vs. Other Intel
164
- Test Mode Select (TMS)
  165
- Test Data Input (TDI)
  165
- Test Data Output (TDO)
  165
Interrupt and Non-Maskable Interrupt Interface
165
- Interrupt Logic
  166
- NMI Logic
  166
- SMI# Logic
  166
- STPCLK# Logic
  167
Write Buffers
167
Reordering of a Reads with Write Buffers
168
- Write Buffers and I/O Cycles
  169
- Write Buffers on Locked Bus Cycles
  169
Reset and Initialization
169
- Floating-Point Register Values
  170
Register Values after Reset
170
Floating-Point Values after Reset
170
- Pin State During Reset
  171
Pin States During RESET
172
- Controlling the CLK Signal in the Processor During Power on
  173
- FERR# Pin State During Reset for Intel
  174
FERR# Pin State after Reset and before FP Instructions
174
- Pin State During Stop Grant
  175
Clock Control
174
- Power down Mode (In-Circuit Emulator Support)
  174
- Stop Grant Bus Cycles
  174
Stop Clock Protocol
175
Pin State During Stop Grant Bus State
175
- Grant State
  176
- Clock Control State Diagram
  177
  - Normal State
    177
  - Stop Grant State
    177
  - Intel ® Quark Soc X1000 Core Stop Clock State Machine
    178
  - Stop Clock State
    179
  - Auto HALT Power down State
    179
  - Stop Clock Snoop State (Cache Invalidations)
    179
Recognition of Inputs When Exiting Stop Grant State
179
- Auto Idle Power down State
  180
- Write-Back Enhanced Intel
  180
  - Normal State
    180
  - Stop Grant State
    181
Write-Back Enhanced Intel (Enhanced Bus Configuration)
181
Bus Operation
184
- Data Transfer Mechanism
  184
  - Memory and I/O Spaces
    184
Byte Enables and Associated Data and Operand Bytes
184
- Memory and I/O Space Organization
  185
Physical Memory and I/O Spaces
185
Generating A[31:0] from BE[3:0]# and A[31:A2]
185
- Dynamic Data Bus Sizing
  186
Physical Memory and I/O Space Organization
186
- Interfacing with 8-, 16-, and 32-Bit Memories
  187
Next Byte Enable Values for Bsx# Cycles
187
Data Pins Read with Different Bus Sizes
187
Intel ® Quark Soc X1000 Core with 32-Bit Memory
188
Addressing 16- and 8-Bit Memories
188
Generating A1, BHE# and BLE# for Addressing 16-Bit Devices
189
Logic to Generate A1, BHE# and BLE# for 16-Bit Buses
190
- Dynamic Bus Sizing During Cache Line Files
  191
Data Bus Interface to 16- and 8-Bit Memories
191
Quark Soc X1000 Core Byte Enables
191
- Operand Alignment
  192
Transfer Bus Cycles for Bytes, Words and Dwords
192
- Bus Arbitration Logic
  193
Single Master Intel Quark Core System
193
Single Intel Quark Core with DMA
194
Single Intel Quark Core with Multiple Secondary Masters
195
- Bus Functional Description
  196
  - Non-Cacheable Non-Burst Single Cycles
    196
    
    No Wait States
    196
    
    Inserting Wait States
    197
Basic 2-2 Bus Cycle
197
- Multiple and Burst Cycle Bus Transfers
  198
  - Burst Cycles
    198
Basic 3-3 Bus Cycle
198
- Terminating Multiple and Burst Cycle Transfers
  199
- Non-Cacheable, Non-Burst, Multiple Cycle Transfers
  200
Non-Cacheable, Non-Burst, Multiple-Cycle Transfers
200
- Non-Cacheable Burst Cycles
  200
- Cacheable Cycles
  201

Intel Quark SoC X1000 Design Manual (186 pages)

Brand: Intel | Category: Computer Hardware | Size: 6 MB

Intel Quark SoC X1000 User Manual (26 pages)

Debug Operations

Brand: Intel | Category: Computer Hardware | Size: 0 MB

Table of Contents
2
1 Introduction

4
- Figure 1. Intel Quark Soc X1000
  4
  - Terminology
    5
  - Related Documents
    5
  - Table 1. Terminology
    5
  - Table 2. Related Documents
    5
2 JTAG Interface

7
- SKU-Based JTAG Debug Capability
  7
- CLTAPC Instruction Table
  7
- Table 3. CLTAPC TAP Instructions
  7
- CLTAPC Data Register Table
  8
  - Clidcode
    8
  - Clbypass
    8
  - Cltapc_Select
    8
  - Table 4. CLTAPC TAP Data Registers
    8
  - Cltapc_Cpu_Vpreq
    9
  - Cltapc_Cpu_Tapstatus
    10
  - Cltapc_Cpu_Vprdy
    10
  - Cltapc_Tapnw_Status
    10
  - Table 6. CLTAPC_CPU_VPREQ
    10
- Cltapc_Tapnw_Status
  11
3 Putting It All Together

12
- Initial JTAG Discovery
  12
- Check Core Powergood
  12
- Add Core TAP to the JTAG Chain
  12
- Verify Core IDCODE
  13
4 JTAG Interface

14
- TAP Instruction Table
  14
- Table 9. TAP Instructions
  14
5 Run Control

15
- Introduction to Probe Mode
  15
- Probe Mode Entry
  15
- Probe Mode Exit
  16
- Reset Break
  16
- TAPSTATUS Register
  16
- Table 10. TAPSTATUS Data Register
  16
- Accessing Architectural Registers
  17
  - Submitting Instructions to the Core
    17
    
    Instruction Faults
    17
  - EIP Management
    18
  - DR7 Management
    18
    
    EIP and Software Breakpoints
    18
  - WRITEPIR Register Format
    18
  - Register Read
    19
  - Register Write
    19
  - Special Cases for Register Access
    19
    
    Pmcr
    19
    
    Register Access after HLT Instruction Execution
    19
  - Checking for HALT State
    20
  - Pseudo Opcodes for Architectural Register Access
    20
  - Probe Mode Control Register
    21
  - Table 11. Register Access PIR Values
    21
  - Accessing Model Specific Registers (MSR)
    22
- Reading and Writing Memory
  22
- Reading and Writing I/O Ports
  24
  - I/O Read
    24
  - I/O Write
    24
- Hardware Breakpoints
  25
- Software Breakpoints
  25
- Single Step
  25
- Redirections into Probe Mode
  25
  - Shutdown Break
    25
  - Revision History
    26

Intel Quark SoC X1000 Software User's Manual (54 pages)

Board Support Package (BSP)

Brand: Intel | Category: Motherboard | Size: 0 MB

Intel Quark SoC X1000 User Manual (38 pages)

Board Support Package BSP, Build and Software

Brand: Intel | Category: Computer Hardware | Size: 0 MB

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Intel Quark SoC X1000 Software User's Manual (54 pages)

Table of Contents

1 About this Document

Part 1 of 2 - Building the BSP Software

2 Before You Begin

3 Downloading Software

4 Building the EDKII Software

5 Building the GRUB os Loader [Linux* Build Environment Only]

6 Creating a File System and Building the Kernel Using Yocto Project

7 Building the Linux* Cross Compile Toolchain Using Yocto Project* [Linux Build Environment Only]

8 Creating a Flash Image for the Board [Linux* Build Environment Only]

9 Platform Data Tool

10 Programming Flash on the Board Using Serial Interface

11 Programming Flash on the Board Using Dediprog

12 Booting the Board from SD Card

Part 2 of 2 - Using the BSP Software

13 Capsule Update

14 Capsule Recovery

15 Signing Files (Secure SKU Only) [Linux* Build Environment Only]

16 Enabling the Openocd Debugger

Appendix A

Intel Quark SoC X1000 User Manual (38 pages)

Table of Contents

1 About this Document

2 Before You Begin

3 Downloading Software

4 Building the EDKII Firmware

5 Building the GRUB os Loader [Linux Build Environment Only]

6 Creating a File System and Building the Kernel Using Yocto [Linux Build Environment Only]

7 Building the Linux* Cross Compile Toolchain Using Yocto [Linux Build Environment Only]

8 Creating a Flash Image for the Board [Linux Build Environment Only]

9 Patching Flash Binary Files Using Platform Data File

10 Programming Flash on the Board Using Serial Interface

11 Programming Flash on the Board Using Dediprog

12 Booting the Board from SD Card

13 Capsule Update

14 Capsule Recovery

15 Signing Files (Secure SKU Only) [Linux Build Environment Only]

16 Enabling the Openocd Debugger

Appendix A Related Documents

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