Intel Quark SoC X1000 Manuals

Manuals and User Guides for Intel Quark SoC X1000. We have 5 Intel Quark SoC X1000 manuals available for free PDF download: Developer's Manual, Design Manual, Software User's Manual, User Manual

Intel Quark SoC X1000 Developer's Manual (311 pages)

Brand: Intel | Category: Motherboard | Size: 2.45 MB

3
Revision History
4
Table of Contents
17
About This Manual
- 17
  Manual Contents
- 18
  Notation Conventions
- 19
  Special Terminology
- 20
  Related Documents
21
Intel Quark Soc X1000 Core Overview
- 21
  Intel Quark Core Architecture
- 21
  Intel ® Quark Soc X1000 Core Used in Intel ® Quark Soc X1000
- 21
  Intel ® Quark Soc X1000 Core
22
Architectural Overview
- 22
  Internal Architecture
- 22
  System Architecture
- 22
  Memory Organization
  - 23
    Address Spaces
  - 24
    Segment Register Usage
- 24
  Address Translation
- 25
  I/O Space
- 25
  Addressing Modes
  - 25
    Addressing Modes Overview
25
Segment Register Selection Rules
- 26
  Register and Immediate Modes
- 26
  32-Bit Memory Addressing Modes
- 27
  Addressing Mode Calculations
  - 28
    Differences Between 16- and 32-Bit Addresses
- 28
  Data Types
28
BASE and INDEX Registers for 16- and 32-Bit Addresses
- 29
  Unsigned Data Types
- 29
  Signed Data Types
- 29
  Data Types
  - 30
    BCD Data Types
  - 30
    Floating-Point Data Types
  - 30
    String Data Types
  - 31
    ASCII Data Types
- 31
  Data Types
  - 32
    Pointer Data Types
- 32
  String and ASCII Data Types
  - 33
    Little Endian Vs. Big Endian Data Formats
- 33
  Interrupts
  - 33
    Interrupts and Exceptions
- 33
  Big Vs. Little Endian Memory Format
  - 34
    Interrupt Processing
  - 34
    Maskable Interrupt
  - 35
    Non-Maskable Interrupt
35
Interrupt Vector Assignments
35
FPU Interrupt Vector Assignments
- 36
  Software Interrupts
- 36
  Interrupt and Exception Priorities
- 37
  Instruction Restart
37
Sequence of Exception Checking
- 38
  Double Fault
- 38
  Floating-Point Interrupt Vectors
38
Interrupt Vectors Used By FPU
39
System Register Organization
- 39
  Register Set Overview
- 39
  Floating-Point Registers
- 39
  Base Architecture Registers
  - 40
    General Purpose Registers
40
Base Architecture Registers
- 41
  Instruction Pointer
- 41
  Flags Register
41
Flag Registers
42
Data Type Alignment Requirements
- 44
  Segment Registers
- 44
  Segment Descriptor Cache Registers
- 45
  System-Level Registers
  - 46
    Control Registers
46
System-Level Registers
- 47
  Control Register 0 (CR0)
47
Control Registers
47
On-Chip Cache Control Modes
48
Intel ® Quark Soc X1000 Core Operating Modes
50
Recommended Values of the Floating-Point Related Bits for Intel
50
Interpreting Different Combinations of EM, TS and MP Bits
- 51
  Control Register 1 (CR1)
- 51
  Control Register 2 (CR2)
- 51
  Control Register 3 (CR3)
- 51
  Control Register 4 (CR4)
- 52
  System Address Registers
- 53
  Floating-Point Registers
55
Floating-Point Status Word
56
Condition Code Interpretation After FPREM and FPREM1 Instructions
56
Floating-Point Condition Code Interpretation
57
Condition Code Resulting From Comparison
57
Condition Code Defining Operand Class
- 58
  Instruction and Data Pointers
58
FPU Exceptions
59
Protected Mode FPU Instructions and Data Pointer Image in Memory (32-Bit Format)
59
Real Mode FPU Instruction and Data Pointer Image in Memory (32-Bit Format)
60
Protected Mode FPU Instruction and Data Pointer Image in Memory (16-Bit Format)
60
Real Mode FPU Instruction and Data Pointer Image in Memory (16-Bit Format)
- 61
  FPU Control Word
- 62
  Debug and Test Registers
  - 62
    Debug Registers
  - 62
    Test Registers
- 62
  Register Accessibility
  - 63
    FPU Register Usage
- 63
  Reserved Bits and Software Compatibility
63
Register Usage
63
FPU Register Usage Differences
- 64
  Intel ® Quark Core Model Specific Registers (Msrs)
65
Real Mode Architecture
- 65
  Introduction
65
Instruction Forms in Which LOCK Prefix Is Legal
- 66
  Memory Addressing
- 66
  Reserved Locations
66
Real Address Mode Addressing
- 67
  Interrupts
- 67
  Shutdown and Halt
67
Exceptions with Different Meanings in Real Mode
68
Protected Mode Architecture
- 68
  Addressing Mechanism
- 69
  Segmentation
  - 69
    Segmentation Introduction
69
Protected Mode Addressing
69
Paging and Segmentation
- 70
  Terminology
- 70
  Descriptor Tables
  - 70
    Descriptor Tables Introduction
  - 71
    Global Descriptor Table
  - 71
    Local Descriptor Table
  - 71
    Interrupt Descriptor Table
71
Descriptor Table Registers
- 72
  Descriptors
  - 72
    Descriptor Attribute Bits
  - 72
    Intel ® Quark Core Code, Data Descriptors (S=1)
72
Interrupt Descriptor Table Register Use
73
Segment Descriptors
- 74
  System Descriptor Formats
74
Access Rights Byte Definition for Code and Data Descriptions
- 75
  LDT Descriptors (S=0, TYPE=2)
- 75
  TSS Descriptors (S=0, TYPE=1, 3, 9, B)
- 75
  Gate Descriptors (S=0, TYPE=4-7, C, F)
75
System Segment Descriptors
76
Gate Descriptor Formats
- 77
  Selector Fields
- 77
  Segment Descriptor Cache
- 77
  Segment Descriptor Register Settings
78
Example Descriptor Selection
79
Segment Descriptor Caches for Real Address Mode
80
Segment Descriptor Caches for Protected Mode (Loaded Per Descriptor)
- 81
  Protection
  - 81
    Protection Concepts
81
Segment Descriptor Caches for Virtual 8086 Mode Within Protected Mode
- 82
  Rules of Privilege
- 82
  Privilege Levels
  - 82
    Task Privilege
  - 82
    Selector Privilege (RPL)
82
Four-Level Hierarchical Protection
- 83
  I/O Privilege and I/O Permission Bitmap
84
Intel ® Quark Core TSS and TSS Registers
- 85
  Privilege Validation
- 85
  Descriptor Access
85
Sample I/O Permission Bit Map
85
Pointer Test Instructions
- 86
  Privilege Level Transfers
86
Descriptor Types Used for Control Transfer
- 87
  Call Gates
- 88
  Task Switching
88
Intel ® Quark Core TSS
- 89
  Floating-Point Task Switching
- 89
  Initialization and Transition to Protected Mode
90
Simple Protected System
- 91
  Paging
  - 91
    Paging Concepts
  - 91
    Paging Organization
    - 91
      Page Mechanism
    - 91
      Page Descriptor Base Register
91
GDT Descriptors for Simple System
- 92
  Page Directory
- 92
  Page Tables
- 92
  Page Directory/Table Entries
- 92
  Paging-Mode Modifiers
- 93
  PAE Paging
  - 93
    PDPTE Registers
93
Use of CR3 with PAE Paging
- 94
  Linear-Address Translation with PAE Paging
94
Format of a PAE Page-Directory-Pointer-Table Entry (PDPTE)
95
Linear-Address Translation to a 4-Kbyte Page Using PAE Paging
96
Linear-Address Translation to a 2-Mbyte Page Using PAE Paging
96
Format of a PAE Page-Directory Entry That Maps a 2-Mbyte Page
97
Format of a PAE Page-Directory Entry That References a
97
Format of a PAE Page-Table Entry That Maps a 4-Kbyte Page
98
Formats of CR3 and Paging-Structure Entries in 32-Bit Mode with PAE Paging Disabled
99
Formats of CR3 and Paging-Structure Entries in 32-Bit Mode with PAE Paging Enabled
- 100
  Access Rights
103
Page Cacheability
103
Page Level Protection Attributes
- 104
  Page-Fault Exceptions
104
Translation Lookaside Buffer
105
Page-Fault Error Code
- 106
  Paging Operation
- 107
  Operating System Responsibilities
- 107
  Virtual 8086 Environment
  - 107
    Executing Programs
107
Page Fault System Information
- 108
  Virtual 8086 Mode Addressing Mechanism
- 108
  Paging in Virtual Mode
108
Virtual 8086 Environment Memory Management
- 109
  Protection and I/O Permission Bitmap
- 110
  Interrupt Handling
- 111
  Entering and Leaving Virtual 8086 Mode
111
Virtual 8086 Environment Interrupt and Call Handling
- 112
  Task Switches to and From Virtual 8086 Mode
- 112
  Transitions Through Trap and Interrupt Gates, and IRET
114
On-Chip Cache
- 114
  Cache Organization
114
On-Chip Cache Physical Organization
- 115
  Write-Back Enhanced Intel ® Quark Soc X1000 Core Cache
- 115
  Quark Soc X1000
115
Write-Back Enhanced Intel ® Quark Soc X1000 Core WB/WT# Initialization
- 116
  Cache Control
  - 116
    Write-Back Enhanced Intel Operating Modes
116
Cache Operating Modes
- 117
  Cache Line Fills
- 118
  Cache Line Invalidations
  - 118
    Write-Back Enhanced Intel
    - 118
      Write-Back Mode Invalidation
- 118
  Cache Replacement
- 118
  Quark Soc X1000
118
Write-Back Enhanced Intel Cycle
- 119
  Page Cacheability
  - 119
    Cacheability
119
On-Chip Cache Replacement Strategy
119
Encoding of the Special Cycles for Write-Back Cache
- 121
  Page Cacheability
- 122
  Cache Flushing
  - 122
    Write-Back Enhanced Intel
- 122
  Quark Soc X1000 Core Cache Flushing
- 123
  Write-Back Enhanced Intel
123
Quark Soc X1000 Core Write-Back Cache Architecture
- 123
  Write-Back Cache Coherency Protocol
124
Cache State Transitions for Write-Back Enhanced Intel Core-Initiated Unlocked Read Cycles
- 125
  Detecting On-Chip Write-Back Cache of the Write-Back Enhanced Intel Quark Soc X1000 Core
125
Cache State Transitions for Write-Back Enhanced Intel Core-Initiated Write Cycles
- 125
  Quark Soc X1000
125
Cache State Transitions During Snoop Cycles
127
System Management Mode (SMM) Architectures
- 127
  Terminology
- 128
  System Management Interrupt Processing
128
Basic SMI# Interrupt Service
- 129
  System Management Interrupt (SMI#)
- 129
  SMI# Active (SMIACT#)
129
Basic SMI# Hardware Interface
- 130
  Smram
130
SMI# Timing for Servicing an I/O Trap
- 131
  SMRAM State Save Map
132
Redirecting System Memory Addresses to SMRAM
- 133
  Exit From SMM
- 134
  System Management Mode Programming Model
  - 134
    Entering System Management Mode
  - 135
    Processor Environment
135
Transition to and From System Management Mode
- 136
  Write-Back Enhanced Intel ® Quark Soc X1000 Core Environment
- 136
  Executing System Management Mode Handler
136
SMM Initial Processor Core Register Settings
- 137
  Exceptions and Interrupts Within System Management Mode
- 138
  SMM Features
  - 138
    SMM Revision Identifier
  - 138
    Auto Halt Restart
138
Bit Values for SMM Revision Identifier
- 139
  I/O Instruction Restart
139
Auto HALT Restart
139
Bit Values for Auto HALT Restart
- 140
  SMM Base Relocation
140
SMM Base Location
140
I/O Instruction Restart Value
- 141
  SMM System Design Considerations
  - 141
    SMRAM Interface
141
SMRAM Usage
- 142
  Cache Flushes
142
SMRAM Location
143
FLUSH# Mechanism During SMM
143
Cached SMM
- 144
  Write-Back Enhanced Intel Management Mode and Cache Flushing
144
Non-Cached SMM
144
Cache Flushing (Non-Overlaid SMRAM)
145
Cache Flushing (Overlaid SMRAM)
- 146
  Snoop During SMM
- 146
  A20M# Pin and SMBASE Relocation
- 146
  Processor Reset During SMM
- 147
  SMM and Second-Level Write Buffers
- 147
  Nested Smi#S and I/O Restart
- 147
  SMM Software Considerations
  - 147
    SMM Code Considerations
  - 148
    Exception Handling
  - 148
    Halt During SMM
  - 148
    Relocating SMRAM to an Address Above One Megabyte
149
Hardware Interface
- 149
  Introduction
- 150
  Signal Descriptions
  - 150
    Clock (CLK)
  - 150
    Address Bus (A[31:2], BE[3:0]#)
150
Functional Signal Groupings
- 151
  Data Lines (D[31:0])
- 151
  Parity
  - 151
    Data Parity Input/Outputs (DP[3:0])
  - 151
    Parity Status Output (PCHK#)
  - 152
    Bus Cycle Definition
    - 152
      M/IO#, D/C#, W/R# Outputs
    - 152
      Bus Lock Output (LOCK#)
152
ADS# Initiated Bus Cycle Definitions
- 153
  Pseudo-Lock Output (PLOCK#)
- 153
  PLOCK# Floating-Point Considerations
- 153
  Bus Control
  - 153
    Address Status Output (ADS#)
  - 153
    Non-Burst Ready Input (RDY#)
  - 154
    Burst Control
    - 154
      Burst Ready Input (BRDY#)
    - 154
      Burst Last Output (BLAST#)
  - 154
    Interrupt Signals
  - 154
    Reset Input (RESET)
  - 155
    Soft Reset Input (SRESET)
  - 155
    System Management Interrupt Request Input (SMI#)
  - 155
    System Management Mode Active Output (SMIACT#)
  - 155
    Maskable Interrupt Request Input (INTR)
  - 156
    Non-Maskable Interrupt Request Input (NMI)
  - 156
    Stop Clock Interrupt Request Input (STPCLK#)
- 156
  Bus Arbitration Signals
  - 156
    Bus Request Output (BREQ)
  - 156
    Bus Hold Request Input (HOLD)
  - 157
    Bus Hold Acknowledge Output (HLDA)
  - 157
    Backoff Input (BOFF#)
- 157
  Cache Invalidation
  - 158
    Address Hold Request Input (AHOLD)
  - 158
    External Address Valid Input (EADS#)
- 158
  Cache Control
  - 158
    Cache Enable Input (KEN#)
  - 158
    Cache Flush Input (FLUSH#)
- 159
  Page Cacheability (PWT, PCD)
- 159
  Reserved
- 159
  Numeric Error Reporting (FERR#, IGNNE#)
  - 159
    Floating-Point Error Output (FERR#)
  - 160
    Ignore Numeric Error Input (IGNNE#)
- 160
  Bus Size Control (BS16#, BS8#)
- 161
  Address Bit 20 Mask (A20M#)
  - 161
    Enhanced Bus Features
  - 161
    Cacheability (CACHE#)
161
Differences Between CACHE# and PCD
- 162
  Cache Flush (FLUSH#)
- 162
  Hit/Miss to a Modified Line (HITM#)
162
CACHE# Vs. Other Intel Quark Core Signals
- 163
  Soft Reset (SRESET)
- 163
  Invalidation Request (INV)
163
HITM# Vs. Other Intel
163
INV Vs. Other Intel ® Quark Core Signals
- 164
  Write-Back/Write-Through (WB/WT#)
- 164
  Pseudo-Lock Output (PLOCK#)
- 164
  Test Signals
  - 164
    Test Clock (TCK)
164
WB/WT# Vs. Other Intel
- 165
  Test Mode Select (TMS)
- 165
  Test Data Input (TDI)
- 165
  Test Data Output (TDO)
165
Interrupt and Non-Maskable Interrupt Interface
- 166
  Interrupt Logic
- 166
  NMI Logic
- 166
  SMI# Logic
- 167
  STPCLK# Logic
167
Write Buffers
168
Reordering of a Reads with Write Buffers
- 169
  Write Buffers and I/O Cycles
- 169
  Write Buffers On Locked Bus Cycles
169
Reset and Initialization
- 170
  Floating-Point Register Values
170
Register Values After Reset
170
Floating-Point Values After Reset
- 171
  Pin State During Reset
172
Pin States During RESET
- 173
  Controlling the CLK Signal in the Processor During Power On
- 174
  Power Down Mode (In-Circuit Emulator Support)
- 174
  Stop Grant Bus Cycles
174
FERR# Pin State After Reset and before FP Instructions
- 175
  Pin State During Stop Grant
175
Stop Clock Protocol
175
Pin State During Stop Grant Bus State
- 176
  Grant State
- 177
  Clock Control State Diagram
  - 177
    Normal State
  - 177
    Stop Grant State
  - 178
    Intel ® Quark Soc X1000 Core Stop Clock State Machine
  - 179
    Stop Clock State
  - 179
    Auto HALT Power Down State
  - 179
    Stop Clock Snoop State (Cache Invalidations)
179
Recognition of Inputs When Exiting Stop Grant State
- 180
  Auto Idle Power Down State
- 180
  Write-Back Enhanced Intel
  - 180
    Normal State
  - 181
    Stop Grant State
181
Write-Back Enhanced Intel (Enhanced Bus Configuration)
- 182
  Stop Clock State
- 182
  Auto HALT Power Down State
- 183
  Stop Clock Snoop State (Cache Invalidations)
  - 183
    Auto HALT Power Down Flush State (Cache Flush) for the Write-Back Enhanced Intel Quark Soc X1000 Core
184
Bus Operation
- 184
  Data Transfer Mechanism
  - 184
    Memory and I/O Spaces
184
Byte Enables and Associated Data and Operand Bytes
- 185
  Memory and I/O Space Organization
185
Physical Memory and I/O Spaces
185
Generating A[31:0] From BE[3:0]# and A[31:A2]
- 186
  Dynamic Data Bus Sizing
186
Physical Memory and I/O Space Organization
- 187
  Interfacing with 8-, 16-, and 32-Bit Memories
187
Next Byte Enable Values for Bsx# Cycles
187
Data Pins Read with Different Bus Sizes
188
Intel ® Quark Soc X1000 Core with 32-Bit Memory
188
Addressing 16- and 8-Bit Memories
189
Generating A1, BHE# and BLE# for Addressing 16-Bit Devices
190
Logic to Generate A1, BHE# and BLE# for 16-Bit Buses
- 191
  Dynamic Bus Sizing During Cache Line Files
191
Data Bus Interface to 16- and 8-Bit Memories
191
Quark Soc X1000 Core Byte Enables
- 192
  Operand Alignment
192
Transfer Bus Cycles for Bytes, Words and Dwords
- 193
  Bus Arbitration Logic
193
Single Master Intel Quark Core System
194
Single Intel Quark Core with DMA
195
Single Intel Quark Core with Multiple Secondary Masters
- 196
  Bus Functional Description
  - 196
    Non-Cacheable Non-Burst Single Cycles
    - 196
      No Wait States
    - 197
      Inserting Wait States
197
Basic 2-2 Bus Cycle
- 198
  Multiple and Burst Cycle Bus Transfers
  - 198
    Burst Cycles
198
Basic 3-3 Bus Cycle
- 199
  Terminating Multiple and Burst Cycle Transfers
- 200
  Non-Cacheable, Non-Burst, Multiple Cycle Transfers
200
Non-Cacheable, Non-Burst, Multiple-Cycle Transfers
- 200
  Non-Cacheable Burst Cycles
- 201
  Cacheable Cycles
201
Non-Cacheable Burst Cycle
- 202
  Byte Enables During a Cache Line Fill
- 202
  Non-Burst Cacheable Cycles
- 203
  Burst Cacheable Cycles

Intel Quark SoC X1000 Design Manual (186 pages)

Brand: Intel | Category: Computer Hardware | Size: 6.91 MB

Intel Quark SoC X1000 User Manual (26 pages)

Debug Operations

Brand: Intel | Category: Computer Hardware | Size: 0.53 MB

- 2
  Table of Contents
4
1 Introduction
- 4
  Figure 1. Intel Quark Soc X1000
  - 5
    Terminology
  - 5
    Related Documents
  - 5
    Table 1. Terminology
  - 5
    Table 2. Related Documents
7
2 JTAG Interface
- 7
  Sku-Based JTAG Debug Capability
- 7
  CLTAPC Instruction Table
- 7
  Table 3. CLTAPC TAP Instructions
- 8
  CLTAPC Data Register Table
  - 8
    Clidcode
  - 8
    Clbypass
  - 8
    Cltapc_Select
  - 8
    Table 4. CLTAPC TAP Data Registers
  - 9
    Cltapc_Cpu_Vpreq
  - 10
    Cltapc_Cpu_Tapstatus
  - 10
    Cltapc_Cpu_Vprdy
  - 10
    Cltapc_Tapnw_Status
  - 10
    Table 6. CLTAPC_CPU_VPREQ
- 11
  Cltapc_Tapnw_Status
12
3 Putting It All Together
- 12
  Initial JTAG Discovery
- 12
  Check Core Powergood
- 12
  Add Core TAP to the JTAG Chain
- 13
  Verify Core IDCODE
14
4 JTAG Interface
- 14
  TAP Instruction Table
- 14
  Table 9. TAP Instructions
15
5 Run Control
- 15
  Introduction to Probe Mode
- 15
  Probe Mode Entry
- 16
  Probe Mode Exit
- 16
  Reset Break
- 16
  TAPSTATUS Register
- 16
  Table 10. TAPSTATUS Data Register
- 17
  Accessing Architectural Registers
  - 17
    Submitting Instructions to the Core
    - 17
      Instruction Faults
  - 18
    EIP Management
  - 18
    DR7 Management
    - 18
      EIP and Software Breakpoints
  - 18
    WRITEPIR Register Format
  - 19
    Register Read
  - 19
    Register Write
  - 19
    Special Cases for Register Access
    - 19
      Pmcr
    - 19
      Register Access After HLT Instruction Execution
  - 20
    Checking for HALT State
  - 20
    Pseudo Opcodes for Architectural Register Access
  - 21
    Probe Mode Control Register
  - 21
    Table 11. Register Access PIR Values
  - 22
    Accessing Model Specific Registers (MSR)
- 22
  Reading and Writing Memory
- 24
  Reading and Writing I/O Ports
  - 24
    I/O Read
  - 24
    I/O Write
- 25
  Hardware Breakpoints
- 25
  Software Breakpoints
- 25
  Single Step
- 25
  Redirections Into Probe Mode
  - 25
    Shutdown Break
  - 26
    Revision History

Intel Quark SoC X1000 Software User's Manual (54 pages)

Board Support Package (BSP)

Brand: Intel | Category: Motherboard | Size: 0.73 MB

Intel Quark SoC X1000 User Manual (38 pages)

Board Support Package BSP, Build and Software

Brand: Intel | Category: Computer Hardware | Size: 0.98 MB

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6 Creating a File System and Building the Kernel Using Yocto [Linux Build Environment Only]

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7 Building the Linux* Cross Compile Toolchain Using Yocto [Linux Build Environment Only]

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8 Creating a Flash Image for the Board [Linux Build Environment Only]

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10 Programming Flash On the Board Using Serial Interface

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11 Programming Flash On the Board Using Dediprog

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12 Booting the Board From SD Card

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Appendix A Related Documents

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Intel Quark SoC X1000 Software User's Manual (54 pages)

Table of Contents

Intel Quark SoC X1000 User Manual (38 pages)

Table of Contents

4 1 About This Document

5 2 Before You Begin

7 3 Downloading Software

8 4 Building the EDKII Firmware

13 5 Building the GRUB OS Loader [Linux Build Environment Only]

15 6 Creating a File System and Building the Kernel Using Yocto [Linux Build Environment Only]

18 7 Building the Linux* Cross Compile Toolchain Using Yocto [Linux Build Environment Only]

20 8 Creating a Flash Image for the Board [Linux Build Environment Only]

22 9 Patching Flash Binary Files Using Platform Data File

24 10 Programming Flash On the Board Using Serial Interface

28 11 Programming Flash On the Board Using Dediprog

29 12 Booting the Board From SD Card

31 13 Capsule Update

32 14 Capsule Recovery

33 15 Signing Files (Secure SKU Only) [Linux Build Environment Only]

35 16 Enabling the Openocd Debugger

36 Appendix A Related Documents

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4
1 Introduction

7
2 JTAG Interface

12
3 Putting It All Together

14
4 JTAG Interface

15
5 Run Control

4
1 About This Document

5
2 Before You Begin

7
3 Downloading Software

8
4 Building the EDKII Firmware

13
5 Building the GRUB OS Loader [Linux Build Environment Only]

15
6 Creating a File System and Building the Kernel Using Yocto [Linux Build Environment Only]

18
7 Building the Linux* Cross Compile Toolchain Using Yocto [Linux Build Environment Only]

20
8 Creating a Flash Image for the Board [Linux Build Environment Only]

22
9 Patching Flash Binary Files Using Platform Data File

24
10 Programming Flash On the Board Using Serial Interface

28
11 Programming Flash On the Board Using Dediprog

29
12 Booting the Board From SD Card

31
13 Capsule Update

32
14 Capsule Recovery

33
15 Signing Files (Secure SKU Only) [Linux Build Environment Only]

35
16 Enabling the Openocd Debugger

36
Appendix A Related Documents