Table 5-1. Instruction Encoding Formats - Intel i960 Jx Developer's Manual

INSTRUCTION SET OVERVIEW
5.1.2 Instruction Encoding Formats
All instructions are encoded in one 32-bit machine language instruction — also known as an
opword — which must be word aligned in memory. An opword's most significant eight bits
contain the opcode field. The opcode field determines the instruction to be performed and how the
remainder of the machine language instruction is interpreted. Instructions are encoded in opwords
in one of four formats (see
APPENDIX C, MACHINE-LEVEL INSTRUCTION

Table 5-1. Instruction Encoding Formats

Instruction Type Format
register REG
compare and branch COBR
control CTRL
memory MEM
5-2
Figure 5-1). For more information on instruction formats, see
FORMATS.
Most instructions are encoded in this format. Used primarily
for instructions which perform register-to-register operations.
An encoding optimization which combines compare and
branch operations into one opword. Other compare and
branch operations are also provided as REG and CTRL
format instructions.
Used for branches and calls that do not depend on registers
for address calculation.
Used for referencing an operand which is a memory address.
Load and store instructions — and some branch and call
instructions — use this format. MEM format has two
encodings: MEMA or MEMB. Usage depends upon the
addressing mode selected. Some MEMB-formatted
addressing modes use the word in memory immediately
following the instruction opword as a 32-bit constant. MEMA
format uses one word and MEMB uses one or two words.
Description