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11.6.8.2
Expanded Mode
In expanded mode, up to 240 interrupts can be requested from external sources. Multiple external
sources are externally encoded into the 8-bit interrupt vector number. This vector number is then
applied to the external interrupt pins
least-significant bit and XINT7 the most significant bit of the number. Note that external interrupt
pins are active low; therefore, the inverse of the vector number is actually applied to the pins.
In expanded mode, external logic is responsible for posting and prioritizing external sources.
Typically, this scheme is implemented with a simple configuration of external priority encoders.
The interrupt source must remain asserted until the processor services the interrupt and explicitly
clears the source. As shown in
of the external sources when more than one expanded mode interrupt is pending.
An expanded mode interrupt source must remain asserted until the processor services the interrupt
and explicitly clears the source. External-interrupt pins in expanded mode are always active low
and level-detect. The interrupt controller ignores vector numbers 0 though 7. The output of the
external priority encoders in
are pending.
The low-order four bits of IMAP0 buffer the expanded-mode interrupt internally. XINT[7:4] are
placed in IMAP0[3:0]; XINT[3:0] are latched in a special register for use in further arbitrating the
interrupt and in selecting the interrupt handler.
IMSK register bit 0 provides a global mask for all expanded interrupts. The remaining bits (1-7)
must be set to 0 in expanded mode. Optionally, the mask bit can be saved and cleared when an
expanded mode interrupt is serviced. This allows other hardware-requested interrupts to be locked
out until the mask is restored. IPND register bits 0-7 have no function in expanded mode, since
external logic is responsible for posting interrupts.
IMAP Control Registers
TINT0
TINT1
XINT[7:0]
(Figure
11-5), with the XINT0 pin representing the
Figure
11-6, simple, combinational logic can handle prioritization
Figure 11-6
can use the 0 vector to indicate that no external interrupts
Hard-wired Vector Offset
PPPP
PPPP
4 MSB
Figure 11-5. Expanded Mode
INTERRUPTS
0010
2
0010
2
4 LSB
Highest Selected
Vector Number
8
11
11-15
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