Bus Control (Bcon) Register; Figure 13-3. Bus Control Register (Bcon) - Intel i960 Jx Developer's Manual

MEMORY CONFIGURATION
13.4.1

Bus Control (BCON) Register

Immediately after a hardware reset, the PMCON register contents are marked invalid in the Bus
Control (BCON) register. Figure 13-3
bit. Whenever the PMCON entries are marked invalid in BCON, the BCU uses the parameters in
PMCON14_15 for all regions. On a hardware reset, PMCON14_15 is automatically cleared. This
operation configures all regions to an 8-bit bus width. Subsequently, the processor loads all
PMCON registers from the Control Table. The processor then loads BCON from the Control
Table. If BCON.ctv is clear, then PMCON14_15 will remain in use for all bus accesses. If
BCON.ctv is set, the region table is valid and the BCU uses the programmed PMCON values for
each region.
Configuration Entries in Control Table Valid (BCON.ctv)
0 = PMCON entries not valid, default to PMCON14_15 setting.
1 = PMCON entries valid
Internal RAM Protection (BCON.irp)
0 = Internal data RAM not protected from user mode writes
1 = Internal data RAM protected from user mode writes
Supervisor Internal RAM Protection (BCON.sirp)
0 = First 64-bytes not protected from supervisor mode writes
1 = First 64-bytes protected from supervisor mode writes
28
31
Reserved,
write to zero
Mnemonic Name
Supervisor Internal RAM
SIRP
Protect
IRP Internal RAM Protect
CTV Configuration Table Valid

Figure 13-3. Bus Control Register (BCON)

13-6
shows the BCON register and Control Table Valid (CTV)
24 20 16
Bit #
0 = first 64 bytes not protected from supervisor
2
1 = first 64 bytes protected from supervisor
0 = internal data RAM not protected from user
1
1 = internal data RAM protected from user
0 = PMCON table not valid (use
0
1 = PMCON table valid
12 8 4
Function
mode writes
mode writes
mode writes
mode writes
PMCON14_15 for all access)
S
I
C
I
R
T
R
P
V
P
0