Figure D-12. Tmr0-1 (Timer Mode Register; Figure D-13. Tcr0-1 (Timer Count Register - Intel i960 Jx Developer's Manual

Microprocessor
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REGISTER AND DATA STRUCTURES
Terminal Count Status - TMRx.tc
(0) No Terminal Count
(1) Terminal Count
Timer Enable - TMRx.enable
(0) Disabled
(1) Enabled
Timer Auto Reload Enable - TMRx.reload
(0) Auto Reload Disabled
(1) Auto Reload Enabled
Timer Register Supervisor Write Control - TMRx.sup
(0) Supervisor and User Mode Write Enabled
(1) Supervisor Mode Only Write Enabled
Timer Input Clock Selects - TMRx.csel1:0
(00) 1:1 Timer Clock = Bus Clock
(01) 2:1 Timer Clock = Bus Clock / 2
(10) 4:1 Timer Clock = Bus Clock / 4
(11) 8:1 Timer Clock = Bus Clock / 8
31
28
Timer Mode Register (TMR0, TMR1)
Reserved
(Initialize to 0)

Figure D-12. TMR0-1 (Timer Mode Register)

Section 10.1.1, "Timer Mode Registers (TMR0, TMR1)" (pg. 10-3)
Timer Count Value - TCRx.d31:0
D31:0
28
24
Timer Count Register (TCR0, TCR1)

Figure D-13. TCR0-1 (Timer Count Register)

Section 10.1.2, "Timer Count Register (TCR0, TCR1)" (pg. 10-6)
D-12
24
20
16
20
16
12
8
4
12
8
4
0
0

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