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MEMORY CONFIGURATION
13.6.6.3
Accesses Across LMT Boundaries
Accesses that cross LMT boundaries should be avoided. These accesses are unaligned and broken
into a number of smaller aligned accesses, which reside in one or the other LMT, but not both.
Each smaller access is completed using the parameters of the LMT in which it resides.
13.6.7
Modifying the LMT Registers
An LMT register can be modified using
cache coherency and order the modification with previous and subsequent data accesses.
13.6.8
Dynamic Byte Order Changing
Programmed byte order changes take effect immediately. The next instruction fetch will use the
new byte order setting. This byte-swapping usually results in errors because the current instruction
stream uses the previous byte order setting.
Dynamically changing the byte order to perform limited operations is possible if the code
sequence is locked in the instruction cache. The application must ensure that code executes from
within the locked region (including faults and interrupts) while the opposite byte order is in effect.
The following example illustrates this method:
safe_addr:
lda
mov
icctl
ld
notbit
st
. . .
<Short code sequence>
. . .
st
icctl
In most cases, it is safer to retain the original byte order and use the bswap instruction to convert
data between little-endian and big-endian byte order.
13-14
or
instructions. Both instructions ensure data
st
sysctl
safe_addr,r4
1,r5
0x3,r4,r5
# Lock code in cache.
DLMCON_MM,r6
0,r6,r7
r7,DLMCON_MM
# Toggle byte order.
r6,DLMCON_MM
# Restore byte order.
2,0,r6
# Invalidate cache
# to unlock code.
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