Figure 14-12. Burst Read/Write Transactions With 1,0 Wait States, Extra Tr State - Intel i960 Jx Developer's Manual

Ta
CLKIN
ADDR
AD31:0
ALE
ADS
A3:2
BE1/A1
BE3/BHE
BE0/BLE
WIDTH1:0
D/C
W/R
BLAST
DT/R
DEN
RDYRCV
Figure 14-12. Burst Read/Write Transactions with 1,0 Wait States, Extra Tr State on Read,
Tw Td Td Tr Tr
D
D
In
In
00,01,10, or 11
0 1
01
16-Bit Bus
EXTERNAL BUS
Ta Tw Td Td Tr
DATA DATA
ADDR
Out Out
00,01,10, or 11
0 1
01
14
F_XL034A
14-21