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MEMORY CONFIGURATION
13.1.2
Logical Memory Attributes
The i960 Jx provides a mechanism for defining two logical memory templates (LMTs). An LMT
may be used to specify the logical memory attributes for a section (or subset) of a physical
memory subsystem connected to the BCU (e.g., DRAM, SRAM). The logical memory attributes
defined by the i960 Jx are byte ordering and whether the information is cacheable or
non-cacheable in the on-chip data cache.
There are typically several different LMTs defined within a single memory subsystem. For
example, data within one area of DRAM may be non-cacheable while data in another area is
cacheable.
Figure 13-1
shows the use of the Control Table (PMCON registers) with logical
memory templates for a single DRAM region in a typical application.
PMCON Registers
Region 14_15
Region 12_13
Region 10_11
Region 8_9
Region 6_7
Region 4_5
Region 2_3
Region 0_1
Note: DLMCON maps the remaining memory to cacheable.
Figure 13-1. PMCON and LMCON Example
13-2
FFFF FFFFH
Physical
Regions 10_11
to 14_15
9FFF FFFFH
Non-Cacheable
Physical
Region 8_9
32-bit wide
DRAM
Non-Cacheable
8000 0000H
Physical
Regions 0_1
to 6_7
0000 0000H
Logical Memory
Templates
(LMCON)
LMADR0
LMMAR0
LMADR1
LMMAR1
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