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12.3.2.1
AC Initial Image
The AC initial image is loaded into the on-chip AC register during initialization. The AC initial
image allows the initial value of the overflow mask, no imprecise faults bit and condition code bits
to be selected at initialization.
The AC initial image condition code bits can be used to specify the source of an initialization or
reinitialization when a single instruction entry point to the user startup code is desirable. This is
accomplished by programming the condition code in the AC initial image to a different value for
each different entry point. The user startup code can detect the condition code values — and thus
the source of the reinitialization — by using the compare or compare-and-branch instructions.
12.3.2.2
Fault Configuration Word
The fault configuration word allows the operation-unaligned fault to be masked when an unaligned
memory request is issued. (See
unaligned memory requests.) Whenever an unaligned access is encountered, the processor always
performs the access. After performing the access, the processor determines whether it should
generate a fault. If bit 30 in the fault configuration word is set, a fault is not generated after an
unaligned memory request is issued. If bit 30 is clear, a fault is generated after an unaligned
memory request is performed. An application may elect to generate a fault to detect unwanted
unaligned access. Note that unaligned accesses to MMR space are not affected by bit 30, are never
performed and always causes an operation.unimplemented fault.
12.3.2.3
Instruction Cache Configuration Word
The instruction cache configuration word allows the instruction cache to be enabled or disabled at
initialization. If bit 16 in the instruction cache configuration word is set, the instruction cache is
disabled and all instruction fetches are directed to external memory. Disabling the instruction
cache is useful for tracing execution in a software debug environment. The instruction cache
remains disabled until one of three operations is performed:
•
The processor is reinitialized with a new value in the instruction cache configuration word
•
is issued with the enable instruction cache operation
icctl
•
is issued with the configure instruction cache message type and a cache configuration
sysctl
mode other than disable cache
12.3.2.4
Register Cache Configuration Word
The register cache configuration word specifies the number of free frames in the local register
cache that can be used by non-critical code — code that is either in the executing state (non-inter-
rupted) or code which is in the interrupted state, but, has a process priority less than 28 — must
reserve for critical code (interrupted state and process priority greater than or equal to 28).
INITIALIZATION AND SYSTEM REQUIREMENTS
section 14.2.5, "Data Alignment" (pg. 14-22)
for a description of
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