Table of Contents
Advertisement
12.6.6.1
Output Pins
All output pins on the i960 Jx processor are three-state outputs. Each output can drive a logic 1
(low impedance to V
); a logic 0 (low impedance to V
CC
V
and V
). Each pin can drive an appreciable external load. Refer to
CC
SS
Documents" (pg.
1-10). Specific information on drive capability, timing and derating information,
to calculate output delays based on pin loading, can be found in these documents.
12.6.6.2
Input Pins
All i960 Jx processor inputs are designed to detect TTL thresholds, providing compatibility with
the vast amount of available random logic and peripheral devices that use TTL outputs.
Most i960 Jx processor inputs are synchronous inputs
have a valid level (TTL logic 0 or 1) when the value is used by internal logic. If the value is not
valid, it is possible for a metastable condition to be produced internally resulting in undetermined
behavior. Refer to
section 1.4, "Related Documents" (pg.
valid setup and hold times relatives to CLKIN can be found in the documents.
Synchronous Inputs
(sampled by CLKIN)
AD31:0
RDYRCV
HOLD
TDI
TMS
i960 Jx processor inputs which are considered asynchronous are internally synchronized to the
rising edge of CLKIN. Since they are internally synchronized, the pins only need to be held long
enough for proper internal detection. In some cases, it is useful to know if an asynchronous input
will be recognized on a particular CLKIN cycle or held off until a following cycle. The i960 Jx
microprocessor data sheet provides setup and hold requirements relative to CLKIN which ensure
recognition of an asynchronous input. The data sheets also supply hold times required for detection
of asynchronous inputs.
The ONCE and STEST inputs are asynchronous inputs. These signals are sampled and latched on
the rising edge of the RESET input instead of CLKIN.
INITIALIZATION AND SYSTEM REQUIREMENTS
); or float (present a high impedance to
SS
(Table
12-7). A synchronous input pin must
1-10). Specific information on input
Table 12-7. Input Pins
Asynchronous Inputs
(sampled by CLKIN)
RESET
XINT7:0
NMI
section 1.4, "Related
Asynchronous Inputs
(sampled by RESET)
STEST
LOCK\ONCE
12-37
12
Advertisement
Table of Contents
