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Instruction
Opcode
/ Requisite
idcode is used in conjunction with the device identification register. It connects
the identification register between TDI and TDO in the Shift_DR state. When
idcode
selected, idcode parallel-loads the hard-wired identification code (32 bits) on
TDO into the identification register on the rising edge of TCK in the Capture_DR
0010 2
IEEE 1149.1
state.
Optional
NOTE
on TDI.
bypass instruction selects the Bypass register between TDI and TDO pins while
in SHIFT_DR state, effectively bypassing the processor's test logic. 0 2 is
bypass
captured in the CAPTURE_DR state. This is the only instruction that accesses
1111 2
the Bypass register. While this instruction is in effect, all other test data registers
IEEE 1149.1
have no effect on the operation of the system. Test data registers with both test
Required
and system functionality perform their system functions when this instruction is
selected.
runbist selects the one-bit RUNBIST register, loads a value of 1 into it and
connects it to TDO. It also initiates the processor's built-in self test (BIST) feature
which is able to detect approximately 82% of the stuck-at faults on the device.
The processor AC/DC specifications for V
RESET must be de-asserted prior to executing runbist.
After loading runbist instruction code into the instruction register, the TAP
runbist
controller must be placed in the Run-Test/Idle state.
i960 Jx
rising edge of TCK after the Run-Test/Idle state is entered. The TAP controller
0111 2
must remain in the Run-Test/Idle state until
Processor
approximately 414,000 core cycles to complete
Optional
RUNBIST register's. The results are stored in bit 0 of the RUNBIST register.
After the report completes, the value in the RUNBIST register is shifted out on
TDO during the Shift-DR state. A value of 0 being shifted out on TDO indicates
bist
completes, the processor must be recycled through the reset state to begin
normal operation.
15.3.5
TAP Controller
The TAP controller is a 16-state synchronous finite state machine that controls the sequence of test
logic operations. The TAP can be controlled via a bus master. The bus master can be either
automatic test equipment or a component (i.e. PLD) that interfaces to the Test Access Port (TAP).
The TAP controller changes state only in response to a rising edge of TCK or power-up. The value
of the test mode state (TMS) input signal at a rising edge of TCK controls the sequence of state
changes. The TAP controller is automatically initialized on powerup. In addition, the TAP
controller can be initialized by applying a high signal level on the TMS input for five TCK periods.
Behavior of the TAP controller and other test logic in each controller state is described in the
following subsections. For greater detail on the state machine and the public instructions, refer to
IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture Document.
Description
: The device identification register is not altered by data being shifted in
completed successfully. A value of 1 indicates a failure occurred. After
TEST FEATURES
and CLKIN must be met and
CC
bist
begins on the first
bist
is completed. runbist requires
bist
and report the result to the
bist
15
15-9
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