Data-Specific Registers; Flash Data Register; Intel Xscale ® Data Registers - Intel PXA27 Series Design Manual

26.4.4.3

Data-Specific Registers

Data-specific registers are used for software debugging and to initialize the processor instruction
cache. For more information, refer to these subsections in
®
Intel PXA27x Processor Family Developers Manual:
•
Section 26.5.2, "Debug Control and Status Register (DCSR)"
•
Section 26.4.6.1.1, "SEL_DCSR JTAG Command and Register"
•
Section 26.4.6.3.1 "LDIC JTAG Data Register"
•
Section 26.4.6.1.2, "DBG_TX JTAG Command and Register"
•
Section 26.4.6.1.4, "DBG_RX Data Register"
26.4.4.4

Flash Data Register

The flash data register is a subset of the boundary-scan register. This subset of cells pertinent to
flash programming facilitates shorter programming times using JTAG. The output signals and pins
required for external flash programming are ordered from TDI to TDO as:
←
TDO
For instructions that utilize the flash data register, nBATT_FAULT, nVCC_FAULT, and nRESET
must be de-asserted.
26.4.4.5 Intel XScale
Intel XScale
with the user-defined JTAG instructions that are described in the Intel XScale
Manual.
®
Intel PXA27x Processor Family Design Guide
MA<25:0>
nSDCAS
nOE
SDCLK0
RDnWR
DQM<3:2>_output_enable
MD<31:16>_output_enable
nOE_nCS0_output_enable
®
Data Registers
®
Technology data registers are not documented here. They are used in conjunction
Chapter 26, "Software Debug,"
←
MD<31:0>
←
nWE
←
nCS0
←
DQM<3:0>
←
MA<25:0>_nSDCAS_RDnWR_
DQM<1:0>_output_enable
←
MD<15:0>_output_enable
←
nWE_output_enable
←
SDCLK0_output_enable
JTAG Debug
of the
←
TDI
®
Core Developer's
II:26-9