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15.3.5.3
Select-DR-Scan State .................................................................................. 15-10
15.3.5.4
Capture-DR State ......................................................................................... 15-10
15.3.5.5
Shift-DR State .............................................................................................. 15-11
15.3.5.6
Exit1-DR State ............................................................................................. 15-11
15.3.5.7
Pause-DR State ........................................................................................... 15-11
15.3.5.8
Exit2-DR State ............................................................................................. 15-11
15.3.5.9
Update-DR State .......................................................................................... 15-12
15.3.5.10
Select-IR Scan State .................................................................................... 15-12
15.3.5.11
Capture-IR State .......................................................................................... 15-12
15.3.5.12
Shift-IR State ................................................................................................ 15-12
15.3.5.13
Exit1-IR State ............................................................................................... 15-13
15.3.5.14
Pause-IR State ............................................................................................. 15-13
15.3.5.15
Exit2-IR State ............................................................................................... 15-13
15.3.5.16
Update-IR State ........................................................................................... 15-13
15.3.6
Boundary-Scan Register ..................................................................................... 15-14
15.3.6.1
Example ....................................................................................................... 15-15
15.3.7
Boundary Scan Description Language Example ................................................. 15-18
APPENDIX A
CONSIDERATIONS FOR WRITING PORTABLE CODE
A.1
CORE ARCHITECTURE .................................................................................................. A-1
A.2
ADDRESS SPACE RESTRICTIONS ............................................................................... A-2
A.2.1
Reserved Memory ..................................................................................................... A-2
A.2.2
Initialization Boot Record ........................................................................................... A-2
A.2.3
Internal Data RAM ..................................................................................................... A-2
A.2.4
A.3
Data and Data Structure Alignment.................................................................................. A-3
A.4
RESERVED LOCATIONS IN REGISTERS AND DATA STRUCTURES......................... A-4
A.5
INSTRUCTION SET ......................................................................................................... A-4
A.5.1
Instruction Timing ...................................................................................................... A-4
A.5.2
Implementation-Specific Instructions ......................................................................... A-5
A.6
EXTENDED REGISTER SET........................................................................................... A-5
A.7
A.8
MEMORY CONFIGURATION .......................................................................................... A-6
A.9
INTERRUPTS .................................................................................................................. A-6
A.10
OTHER i960 Jx PROCESSOR IMPLEMENTATION-SPECIFIC FEATURES.................. A-6
A.10.1
Data Control Peripheral Units .................................................................................... A-7
A.10.2
Timers ....................................................................................................................... A-7
A.10.3
Fault Implementation ................................................................................................. A-7
A.11
BREAKPOINTS ................................................................................................................ A-7
APPENDIX B
OPCODES AND EXECUTION TIMES
B.1
INSTRUCTION REFERENCE BY OPCODE ................................................................... B-1
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