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Logical Memory Template Enabled
0 = LMT disabled
1 = LMT enabled
28
24
31
M
M
M
M
M
M
M
M
A
A
A
A
A
A
A
A
3
3
2
2
2
2
2
2
1
0
9
8
7
6
5
4
Reserved,
write to zero
Mnemonic
Bit/Bit Field Name
Template Address
MA31:12
Mask
Logical Memory
LMTE
Template Enabled
Figure 13-5. Logical Memory Template Mask Registers (LMMR0-1)
20
16
M
M
M
M
M
M
M
M
M
M
M
A
A
A
A
A
A
A
A
A
A
A
2
2
2
2
1
1
1
1
1
1
1
3
2
1
0
9
8
7
6
5
4
3
Bit Position(s)
Defines upper 20 bits for the address mask
for a logical memory template. The lower 12
bits are fixed at zero.
31-12
0 = Mask
1 = Do not mask
Enables/disables logical memory template.
0
0 = LMT disabled
1 = LMT enabled
MEMORY CONFIGURATION
12
M
A
1
2
8
4
Template Address Mask
Function
L
M
T
E
0
13
13-9
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