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INTERRUPTS
Table 11-2. Location of Cached Vectors in Internal RAM
Vector Number (Binary)
NMI
0001 0010
2
0010 0010
2
0011 0010
2
0100 0010
2
0101 0010
2
0110 0010
2
0111 0010
2
1000 0010
2
1001 0010
2
1010 0010
2
1011 0010
2
1100 0010
2
1101 0010
2
1110 0010
2
1111 0010
2
11.9.2.2
Caching Interrupt Routines and Reserving Register Frames
The time required to fetch the first instructions of an interrupt-handling procedure affects interrupt
response time and throughput. The user can reduce this fetch time by caching interrupt procedures
or portions of procedures in the i960 Jx processor's instruction cache. The
load and lock these procedures into the instruction cache. See
CACHE" (pg. 4-4)
for information on the instruction cache.
To decrease interrupt latency for high priority interrupts (priority 28 and above), software can limit
the number of frames in the local register cache available to code running at a lower priority
(priority 27 and below). This ensures that some number of free frames are available to
high-priority interrupt service routines. See
for more details.
11.9.2.3
Caching the Interrupt Stack
By locating the interrupt stack in cacheable memory, the performance of interrupt returns can be
improved. This is because accesses to the interrupt record by the interrupt return can be satisfied
by the data cache. See
section 13.6, "Programming the Logical Memory Attributes" (pg. 13-8)
details on how to enable data caching for portions of memory.
11-36
Vector Number (Decimal)
248
18
34
50
66
82
98
114
130
146
162
178
194
210
226
242
section 4.2, "LOCAL REGISTER CACHE" (pg.
Internal RAM Address
0000H
0004H
0008H
000CH
0010H
0014H
0018H
001CH
0020H
0024H
0028H
002CH
0030H
0034H
0038H
003CH
icctl
instruction can
section 4.4, "INSTRUCTION
4-2),
for
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