Table of Contents
Advertisement
11.7.5.1
Interrupt Mask (IMSK) and Interrupt Pending (IPND) Registers
The IMSK and IPND registers (see
registers. Bits 0 through 7 of these registers are associated with the external interrupt pins (XINT0
through XINT7) and bits 12 and 13 are associated with the timer-interrupt inputs (TMR0 and
TMR1). All other bits are reserved and should be set to 0 at initialization.
External Interrupt Pending Bits - IPND.xip
(0) No Interrupt
(1) Pending Interrupt
Timer Interrupt Pending Bits - IPND.tip
(0) No Interrupt
(1) Pending Interrupt
28
24
Interrupt Pending Register (Dedicated Mode)
Timer Interrupt Pending Bits - IPND.tip
(0) No Interrupt
(1) Pending Interrupt
28
24
Interrupt Pending Register (Expanded Mode)
External Interrupt Pending Bits - IPND.xip
(0) No Interrupt
(1) Pending Interrupt
Timer Interrupt Pending Bits - IPND.tip
(0) No Interrupt
(1) Pending Interrupt
28
24
Interrupt Pending Register (Mixed Mode)
Figure 11-10. Interrupt Pending (IPND) Register
Figure 11-10
and
Figure
11-11) are both memory-mapped
t
t
i
i
p
p
1
0
20
16
12
t
t
i
i
p
p
1
0
20
16
12
t
t
i
i
p
p
1
0
20
16
12
INTERRUPTS
x
x
x
x
x
x
x
x
i
i
i
i
i
i
i
i
p
p
p
p
p
p
p
p
7
6
5
4
3
2
1
0
8
4
0
8
4
0
x
x
x
i
i
i
p
p
p
5
7
6
8
4
0
RESERVED
(INITIALIZE TO 0)
11-25
11
Advertisement
Table of Contents
