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INITIALIZATION AND SYSTEM REQUIREMENTS
C
B
A
R
S
Source
F_CA080A
Figure 12-11. Series Termination
C
B
A
C
Source
R
12
F_CA081A
Figure 12-12. AC Termination
12.6.9
Latchup
Latchup is a condition in a CMOS circuit in which V
becomes shorted to V
. Intel's CMOS IV
C C
S S
processes are immune to latchup under normal operation conditions. Latchup can be triggered
when the voltage limits on I/O pins are exceeded, causing internal PN junctions to become forward
biased. The following guidelines help prevent latchup:
•
Observe the maximum rating for input voltage on I/O pins.
12-39
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