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Cacheable stores that are less than a word in length are handled differently. Byte and short-word
stores that hit the cache (i.e., are contained in valid words within valid cache lines) do not change
the tag and valid bits. The processor writes the data into the cache and external memory as usual. A
byte or short-word store to an invalid word within a valid cache line leaves the word valid bit
cleared because the rest of the word is still invalid. In these two cases the processor simultaneously
writes the data into the cache and the external memory.
4.5.5
Data Cache Coherency and Non-Cacheable Accesses
The i960 Jx processor ensures that the data cache is always kept coherent with accesses that it
initiates and performs. The most visible application of this requirement concerns non-cacheable
accesses discussed below. However, the processor does not provide data-cache coherency for
accesses on the external bus that it did not initiate. Software is responsible for maintaining
coherency in a multi-processor environment.
An access is defined as non-cacheable when any of the following is true:
1.
The access falls into an address range mapped by an enabled LMCON or DLMCON and the
data-caching enabled bit in the matching LMCON is clear.
2.
The entire data cache is disabled.
3.
The access is a read operation of the read-modify-write sequence performed by an
atadd
instruction.
4.
The access is an implicit read access to the interrupt table to post or deliver a software interrupt.
When the memory location targeted by an
cache, it is invalidated.
When the address for a non-cacheable store matches a tag ("tag hit"), the corresponding cache line
is marked invalid. This is because the word is not actually updated with the value of the store. This
behavior ensures that the data cache never contains stale data in a single-processor system. A
simple case illustrates the necessity of this behavior: a read of data previously stored by a
non-cacheable access must return the new value of the data, not the value in the cache. Because the
processor invalidates the appropriate word in the cache line on a store hit when the cache is
disabled, coherency can be maintained when the data cache is enabled and disabled dynamically.
Data loads or stores invalidate the corresponding lines of the cache even when data caching is
disabled. This behavior further ensures that the cache does not contain stale data.
CACHE AND ON-CHIP DATA RAM
or
instruction is currently in the data
atmod
atadd
4
or
atmod
4-9
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