Uncommon Tcrx And Trrx Conditions; Table 10-7. Uncommon Tmrx Control Bit Settings - Intel i960 Jx Developer's Manual

TIMERS
10.5

UNCOMMON TCRX AND TRRX CONDITIONS

Table 10-4 summarizes the most common settings for programming the timer registers. Under
certain conditions, however, it may be useful to set the Timer Count Register or the Timer Reload
Register to zero before enabling the timer.
conditions are set.

Table 10-7. Uncommon TMRx Control Bit Settings

X 0 0 1
0 0 1 1
0 N 1 1
N 0 1 1
NOTE:
X = don't care
N = a number between 1H and FFFF FFFFH
10-12
Table 10-7 details the conditions and results when these
TMRx.tc and TINTx set, TMR.enable cleared
Timer and auto reload enabled, TINTx not generated and timer enable
remains set.
Timer and auto reload enabled. TINT.x set when TCRx=0. The timer
remains enabled but further TINTx's are not generated.
Timer and auto reload enabled, TINTx not set initially, TCRx = TRRx,
TINTx set when TCRx has completely decremented the value it
loaded from TRRx. TMRx.enable remains set.
Action