Intel i960 Jx Developer's Manual page 577

Microprocessor
Table of Contents

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9-1
mark
and
fmark
9-1
PC and TC registers
9-3
trace-fault-pending flag
10-7
TRR), TRR1
3-19
true/false conditions
12-37
TTL input pins
two-word burst write transaction
U
3-19
unordered numbers
user space family registers and tables
,
3-12
7-19
user stack
3-15
alignment
user supervisor protection model
3-23
supervisor mode resources
3-24
usage
V
11-5
vector entries
11-5
NMI
11-5
structure
W
,
11-28
12-3
warm reset
words
2-3
triple and quad
X
XINT, see external interrupt (XINT) signals
6-120
xnor
6-120
xor
14-14
3-11
3-23
11-18
INDEX
Index-15

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