Table B-9. Mem Format Instruction Encodings - Intel i960 Jx Developer's Manual

Table B-9. MEM Format Instruction Encodings

31 ........24 23 ...19 18 .......14 13 ....... 12 11.................................................. 0
Opcode
31 ....... 24 23 ...19 18 ....... 14 13 ....... 12 .. 11 ....... 10 9....... 7 6 .. 5 4 ....... 0
Opcode
Effective Address
efa = offset opcode
offset( reg ) opcode
( reg ) opcode
disp + 8 (IP) opcode
( reg1 )[ reg2 * scale ] opcode
disp opcode
disp ( reg ) opcode
disp [ reg * scale ] opcode
disp ( reg1 )[ reg2 * scale ] opcode
Opcode Mnemonic
80 ldob
82 stob
84 bx
85 balx
86 callx
88 ldos
8A stos
8C lda
90 ld
92 st
98 ldl
1. The number of cycles required to execute these instructions is based on the addressing mode used (see
Table B-10).
OPCODES AND EXECUTION TIMES
src/dst ABASE Mode
src/dst ABASE
Displacement
dst 0 0
dst reg 1 0
dst reg 0 1
dst 0 1
displacement
dst reg1 0 1
dst 1 1
displacement
dst reg 1 1
displacement
dst
1 1
displacement
dst reg1 1 1
displacement
Cycles to
Opcode
Execute
(See Note 1.) 9A
(See Note 1.) A0
4-7 A2
5-8
9-12 B0
(See Note 1.) B2
(See Note 1.) C0
(See Note 1.) C2
(See Note 1.) C8
(See Note 1.) CA
(See Note 1.)
Offset
Mode Scale 00
offset
offset
0 0 00
0 1 00
1 1 scale 00
0 0 00
0 1 00
scale
1 0 00
1 1 scale 00
Cycles to
Mnemonic
Execute
stl (See Note 1.)
ldt (See Note 1.)
stt (See Note 1.)
ldq (See Note 1.)
stq (See Note 1.)
ldib (See Note 1.)
stib (See Note 1.)
ldis (See Note 1.)
stis (See Note 1.)
B
Index
reg2
reg
reg2
B-9