Figure 5-1. Machine-Level Instruction Formats; C.3 Cobr Format; Table C-2. Encoding Of Src1 And Src2 In Reg Format; Table C-3. Encoding Of Src/Dst In Reg Format - Intel i960 Jx Developer's Manual

Table C-2. Encoding of src1 and src2 in REG Format

Src1 or Src2 Operand
M1 or M2
0
1
The src/dst field can specify a source operand, a destination operand or both, depending on the
instruction. Here again, mode bit M3 determines how this field is used. If M3 is clear, the src/dst
operand is a global or local register that is encoded as shown in
When a literal is specified, it is always an unsigned 5-bit value that is zero-extended to a 32-bit
value and used as the operand. When the instruction defines an operand to be larger than 32 bits,
values specified by literals are zero-extended to the operand size.

Table C-3. Encoding of src/dst in REG Format

M3 src/dst
g0 ... g15
0
r0 ... r15
1 Reserved
C.3 COBR FORMAT
The COBR format is used primarily for compare-and-branch instructions. The test-if instructions
also use the COBR format. The COBR opcode field is eight bits (two hexadecimal digits).
The src1 and src2 fields specify source operands for the instruction. The src1 field can specify
either a global or local register or a literal as determined by mode bit M1. The src2 field can only
specify a global or local register.
the S2, src2 relationship:.

Table C-4. Encoding of src1 in COBR Format

M1
0
1
MACHINE-LEVEL INSTRUCTION FORMATS
Register Number
Value
00000 ... 01111
10000 ... 11111
00000 ... 11111
src Only
g0 ... g15
r0 ... r15
Reserved
Table C-4 shows the M1, src1 relationship and
Literal Value
r0 ... r15
g0 ... g15
NA
Table C-3.
dst Only
g0 ... g15
r0 ... r15
Reserved
Table C-4
src1
g0 ... g15
r0 ... r15
Literal
NA
NA
C
0 ... 31
shows
C-3