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4.4.2
Operation While the Instruction Cache Is Disabled
Disabling the instruction cache does not disable the instruction buffering that may occur within the
instruction fetch unit. A four-word instruction buffer is always enabled, even when the cache is disabled.
There is one tag and four word-valid bits associated with the buffer. Because there is only one tag
for the buffer, any "miss" within the buffer causes the following:
•
All four words of the buffer are invalidated.
•
A new tag value for the required instruction is loaded.
•
The required instruction(s) are fetched from external memory.
Depending on the alignment of the "missed" instruction, either two or four words of instructions
are fetched and only the valid bits corresponding to the fetched words are set in the buffer. No
external instruction fetches are generated until a "miss" occurs within the buffer, even in the
presence of forward and backward branches.
4.4.3
Loading and Locking Instructions in the Instruction Cache
The processor can be directed to load a block of instructions into one-way of the cache and then
lock out all normal updates to this one-way of the cache. This cache load-and-lock mechanism is
provided to minimize latency on program control transfers to key operations such as interrupt
service routines. The block size that can be loaded and locked on the i960 Jx processor is one way
of the cache. Any code can be locked into the cache, not just interrupt routines.
An
or
instruction is issued with a configure-instruction-cache message type to select
icctl
sysctl
the load-and-lock mechanism. When the lock option is selected, the processor loads the cache
starting at an address specified as an operand to the instruction.
4.4.4
Instruction Cache Visibility
Instruction cache status can be determined by issuing
message. To facilitate debugging, the instruction cache contents, instructions, tags and valid bits
can be written to memory. This is done by issuing
4.4.5
Instruction Cache Coherency
The i960 Jx processor does not snoop the bus to prevent instruction cache incoherency. The cache
does not detect modification to program memory by loads, stores or actions of other bus masters.
Several situations may require program memory modification, such as uploading code at initial-
ization or loading from a backplane bus or a disk drive.
CACHE AND ON-CHIP DATA RAM
with an instruction-cache status
icctl
icctl
with the store cache operation.
4
4-5
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