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INSTRUCTION SET REFERENCE
case 5:
case 6:
default:
STANDARD
Faults:
TYPE.MISMATCH
6-64
# Get instruction cache locking status into dst.
src_dst[7:0] = number_of_blocks_that_lock;
src_dst[23:8] = block_size_in_words;
src_dst[31:24] = number_of_blocks_that_are_locked;
break;
# Store instr cache sets to memory pointed to by src2.
start = src_dst[15:0]
# Starting set number
end = src_dst[31:16]
# Ending set number
# (zero-origin).
if (end >= Icache_max_sets)
end = Icache_max_sets - 1;
if (start > end)
generate_fault(OPERATION.INVALID_OPERAND);
memadr = src2;
# Must be word-aligned.
if(0x3 & memadr != 0)
generate_fault(OPERATION.INVALID_OPERAND);
for (set = start; set <= end; set++){
# Set_Data is described at end of this code flow.
memory[memadr] = Set_Data[set];
memadr += 4;
for (way = 0; way < numb_ways; way++)
{memory[memadr] = tags[set][way];
memadr += 4;
memory[memadr] = valid_bits[set][way];
memadr += 4;
for (word = 0; word < words_in_line;
{memory[memadr] =
memadr += 4;
}
} } break;
# Reserved.
generate_fault(OPERATION.INVALID_OPERAND);
break;}
Refer to
section 6.1.6, "Faults" (pg.
Attempt to execute instruction while not in
supervisor mode.
word++)
Icache_line[set][way][word];
6-5).
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