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INSTRUCTION SET REFERENCE
# before next instruction.
order_wrt(subsequent_operations);
case 1:
case 2:
case 3:
case 4:
6-116
break;
# Global Invalidate Instruction Cache
invalidate_instruction_cache( );
unlock_instruction_cache( );
break;
# Configure Instruction-Cache
mode = src1 & 0xff;
if (mode & 1) disable_instruction_cache;
else switch (mode) {
case 0:
enable_instruction_cache; break;
case 4,6:
# Load & Lock code into I-Cache
# All contiguous blocks are locked.
# Note: block = way on i960 Jx processor.
# src2 has starting address of code to lock.
# src2 is aligned to a quad word
# boundary.
aligned_addr = src2 & 0xfffffff0;
invalidate(I-cache); unlock(I-cache);
for (j = 0; j < number_of_blocks_that_lock; j++)
{way = block_associated_with_block(j);
start = src2 + j*block_size;
end = start + block_size;
for (i = start; i < end; i=i+4)
{
set = set_associated_with(i);
word = word_associated_with(i);
Icache_line[set][way][word] =
update_tag_n_valid_bits(set,way,word)
lock_icache(set,way,word);
} } break;
default:
generate_operation_invalid_operand_fault;
} break;
# Software Re-init
disable(I_cache); invalidate(I_cache);
disable(D_cache); invalidate(D_cache);
Process_PRCB(dst); # dst has ptr to new PRCB
IP = src2;
break;
/* Load One Group of Control Registers From Control Table*/
grpoff = (src1 & 0xff) * 16;
for (i = 0; i < 4; i=i+4)
memory[i];
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