Table of Contents
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This appendix is a compilation of all register and data structure figures described throughout the
manual. Following each figure is a reference that indicates 23the section that discusses the figure.
Table D-1. Register and Data Structures (Sheet 1 of 2)
Fig.
Register / Data Structure
D-1
AC (Arithmetic Controls) Register
D-2
PC (Process Controls) Register
D-3
Procedure Stack Structure and Local Registers
D-4
System Procedure Table
D-5
PFP (Previous Frame Pointer) Register (r0)
D-6
Fault Table and Fault Table Entries
D-7
Fault Record
D-8
TC (Trace Controls) Register
D-9
BPCON (Breakpoint Control) Register
DAB (Data Address Breakpoint) Register
D-10
Format
D-11
IPB (Instruction Breakpoint) Register Format
D-12
TMR0-1 (Timer Mode Register)
D-13
TCR0-1 (Timer Count Register)
D-14
TRR0-1 (Timer Reload Register)
D-15
Interrupt Table
Storage of an Interrupt Record on the Interrupt
D-16
Stack
D-17
ICON (Interrupt Control) Register
D-18
IMAP0-IMAP2 (Interrupt Mapping) Registers
D-19
IMSK (Interrupt Mask) Registers
D-20
Interrupt Pending (IPND) Register
Initial Memory Image (IMI) and Process
D-21
Control Block (PRCB)
REGISTER AND DATA STRUCTURES
Where Defined in the manual
Section 3.7.2, "Arithmetic Controls (AC) Register"
(pg. 3-18)
Section 3.7.3, "Process Controls (PC) Register" (pg. 3-21)
Section 7.1.1, "Local Registers and the Procedure Stack"
(pg. 7-2)
Section 7.5.1, "System Procedure Table" (pg. 7-15)
Section 7.8, "RETURNS" (pg. 7-20)
Section 8.3, "FAULT TABLE" (pg. 8-4)
Section 8.5, "FAULT RECORD" (pg. 8-6)
Section 9.1.1, "Trace Controls (TC) Register" (pg. 9-2)
section 9.2.7.4, "Breakpoint Control Register" (pg. 9-7)
Section 9.2.7.5, "Data Address Breakpoint (DAB) Registers"
(pg. 9-9)
Section 9.2.7.6, "Instruction Breakpoint (IPB) Registers"
(pg. 9-10)
Section 10.1.1, "Timer Mode Registers (TMR0, TMR1)"
(pg. 10-3)
Section 10.1.2, "Timer Count Register (TCR0, TCR1)"
(pg. 10-6)
Section 10.1.3, "Timer Reload Register (TRR0, TRR1)"
(pg. 10-7)
Section 11.4, "INTERRUPT TABLE" (pg. 11-4)
Section 11.5, "INTERRUPT STACK AND INTERRUPT
RECORD" (pg. 11-7)
Section 11.7.4, "Interrupt Control Register (ICON)"
(pg. 11-22)
Section 11.7.5, "Interrupt Mapping Registers
(IMAP0-IMAP2)" (pg. 11-23)
Section 11.7.5.1, "Interrupt Mask (IMSK) and Interrupt
Pending (IPND) Registers" (pg. 11-25)
Section 11.7.5.1, "Interrupt Mask (IMSK) and Interrupt
Pending (IPND) Registers" (pg. 11-25)
Section 12.3.1, "Initial Memory Image (IMI)" (pg. 12-10)
APPENDIX D
D
Page
D-3
D-4
D-5
D-6
D-7
D-8
D-9
D-10
D-10
D-11
D-11
D-12
D-12
D-13
D-14
D-15
D-16
D-17
D-18
D-19
D-20
D-1
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