Bus Arbitration; Figure 14-17. The Lock Signal - Intel i960 Jx Developer's Manual

CLKIN
AD31:0
ALE
ADS
W/R
BLAST
LOCK
RDYRCV
14.2.8

Bus Arbitration

The i960 Jx processor can share the bus with other bus masters, using its built-in arbitration
protocol. The protocol assumes two bus masters: a default bus master (typically the 80960Jx) that
controls the bus and another that requests bus control when it performs an operation (e.g., a DMA
controller). More than two bus masters may exist on the bus, but this configuration requires
external arbitration logic
Three processor signal pins comprise the bus arbitration pin group.
Ta Td Tr Ti
D
Addr Invalid
In

Figure 14-17. The LOCK Signal

EXTERNAL BUS
Ti Ti Ta Td Tr
Data
Addr
Out
14
14-31