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The i960 Jx processor's TAP is composed of four input connections (TMS, TCK, TRST and TDI)
and one output connection (TDO). These pins are described in
Table 15-1. TAP Controller Pin Definitions
Pin Name
Mnemonic
Test Clock
TCK
Test Mode
TMS
Select
Test Data In
TDI
Test Data Out
TDO
Output
Asynchronous
TRST
Reset
15.3
TAP REGISTERS
The instruction and test data registers are separate shift-register paths connected in parallel. The TAP
controller determines which one of these registers is connected between the TDI and TDO pins.
15.3.1
Instruction Register (IR)
The Instruction Register (IR) is a parallel-loadable, master/slave-configured 4-bit wide, serial-shift
register with latched outputs. Data is loaded into the IR serially through the TDI pin clocked by the
rising edge of TCK when the TAP controller is in the Shift_IR state. The shifted-in instruction
becomes active upon latching from the master-stage to the slave-stage in the Update_IR state. At
that time the IR outputs along with the TAP finite state machine outputs are decoded to select and
control the test data register selected by that instruction. Upon latching, all actions caused by any
previous instructions must terminate.
The instruction determines the test to be performed, the test data register to be accessed, or both
(see
Table
15-2). The IR is four bits wide. When the IR is selected in the Shift_IR state, the most
significant bit is connected to TDI, and the least significant bit is connected to TDO. TDI is shifted
into IR on each rising edge of TCK, as long as TMS remains asserted. When the processor enters
Type
Clock input for the TAP controller, the instruction register, and the test
Input
data registers. The JTAG unit will retain its state when TCK is stopped at
"0" or "1".
Controls the operation of the TAP controller. The TMS input is pulled
Input
high when not being driven. TMS is sampled on the rising edge of TCK.
Serial date input to the instruction and test data registers. Data at TDI is
sampled on the rising edge of TCK. Like TMS, TDI is pulled high when
Input
not being driven. Data shifted from TDI through a register to TDO
appears non-inverted at TDO.
Used for serial data output. Data at TDO is driven at the falling edge of
TCK and provides an inactive (high-Z) state when scanning is not in
progress. The non-shift inactive state is provided to support parallel
connection of TDO outputs at the board or module level.
Provides asynchronous initialization of the test logic. TRST is pulled high
when not being driven. Assertion of this pin puts the TAP controller in the
Input
Test_Logic_Reset (initial) state. For minimum pulse width specifications,
see related documents in
TEST FEATURES
Table
15-1.
Definition
section 1.4, "Related Documents" (pg.
1-10).
15
15-5
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