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INTERRUPTS
The IPND register posts dedicated-mode interrupts originating from the eight external dedicated
sources (when configured in dedicated mode) and the two timer sources. Asserting one of these
inputs causes a 1 to be latched into its associated bit in the IPND register. In expanded mode, bits 0
through 7 of this register are not used and should not be modified; in mixed mode, bits 0 through 4
are not used and should not be modified.
The mask register provides a mechanism for masking individual bits in the IPND register. An
interrupt source is disabled if its associated mask bit is set to 0.
Mask register bit 0 has two functions: it masks interrupt pin XINT0 in dedicated mode and it masks
all expanded-mode interrupts globally in expanded and mixed modes. In expanded mode, bits 1
through 7 are not used and should contain zeros only; in mixed mode, bits 1 through 4 are not used
and should contain zeros only.
When delivering a hardware interrupt, the interrupt controller conditionally clears IMSK based on
the value of the ICON.mo bit. Note that IMSK is never cleared for NMI or software interrupt.
Although software can read and write IPND and IMSK using any memory-format instruction, a
read-modify-write operation on these registers must be performed using the atomic-modify
instruction (ATMOD). Executing an ATMOD on one of these registers causes the interrupt
controller to perform regular interrupt processing (including using or automatically updating IPND
and IMSK) either before or after, but not during the read-modify-write operation on that register.
This requirement ensures that modifications to IPND and IMSK take effect cleanly, completely,
and at a well-defined point. Note that the processor does not assert the LOCK pin externally when
executing an atomic instruction to IPND and IMSK.
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When the processor core handles a pending interrupt, it attempts to clear the bit that is latched for that
interrupt in the IPND register before it begins servicing the interrupt. If that bit is associated with an
interrupt source that is programmed for level detection and the true level is still present, the bit
remains set. Because of this, the interrupt routine for a level-detected interrupt should clear the
external interrupt source and explicitly clear the IPND bit before return from the handler is executed.
An alternative method of posting interrupts in the IPND register, other than through the external
interrupt pins, is to set bits in the register directly using an ATMOD instruction. This operation has the
same effect as requesting an interrupt through the external interrupt pins. The bit set in the IPND
register must be associated with an interrupt source that is programmed for dedicated-mode operation.
11.7.5.2
Interrupt Controller Register Access Requirements
Like all other load accesses from internal memory-mapped registers, once issued, a load
instruction that accesses an interrupt register has a latency of one internal processor cycle.
A store access to an interrupt register is synchronous with respect to the next instruction; that is, the
operation completes fully and all state changes take effect before the next instruction begins execution.
11-27
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