Figure D-26. Bcon (Bus Control) Register; Figure D-27. Dlmcon (Default Logical Memory Configuration) Register - Intel i960 Jx Developer's Manual

Microprocessor
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REGISTER AND DATA STRUCTURES
Configuration Entries in Control Table Valid (BCON.ctv)
0 = PMCON entries not valid; use PMCON15 setting.
1 = PMCON entries valid
Internal RAM Protection (BCON.irp)
0 = Internal data RAM not protected from user mode writes
1 = Internal data RAM protected from user mode writes
Supervisor Internal RAM Protection (BCON.sirp)
0 = First 64 bytes not protected from supervisor mode writes
1 = First 64 bytes protected from supervisor mode writes
28
31
Reserved,
write to zero

Figure D-26. BCON (Bus Control) Register

Section 13.4.1, "Bus Control (BCON) Register" (pg. 13-6)
Byte Order
0 = Little endian
1 = Big endian
Data Cache Enabled
0 = Data caching disabled
1 = Write-through caching enabled
28
24
31
Reserved,
write to zero

Figure D-27. DLMCON (Default Logical Memory Configuration) Register

Section 13.6, "Programming the Logical Memory Attributes" (pg. 13-8)
D-24
24
20
16
20
16
12
8
4
12
8
4
S
I
C
I
R
T
R
P
V
P
0
D
C
B
E
E
N
0

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