Figure 14-10. Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus - Intel i960 Jx Developer's Manual

EXTERNAL BUS
Ta
CLKIN
AD31:0
ADDR
ALE
ADS
A3:2
BE3:0
WIDTH1:0
D/C
W/R
BLAST
DT/R
DEN
RDYRCV

Figure 14-10. Burst Write Transactions With 2,1,1,1 Wait States, 32-bit Bus

14-18
Tw Tw Td Tw Td
DATA
DATA
Out
Out
0 0
0 1
1 0
Tw Td Tw Td Tr
DATA
DATA
Out
Out
1 0 1 1
F_XL032A