Intel PXA27 Series Manuals

Manuals and User Guides for Intel PXA27 Series. We have 2 Intel PXA27 Series manuals available for free PDF download: Design Manual, Quick Start Manual

Intel PXA27 Series Design Manual (298 pages)

Brand: Intel | Category: Computer Hardware | Size: 3.82 MB

Table of Contents

3
Table of Contents

15
- Document Organization and Overview
  19
- Introduction to Part I
  19
- Functional Overview
  20
- Pxa27X Processor Block Diagram
  20
  - Package Introduction
    21
  - Signal Pin Descriptions
    22
- Part I
  
  23
- Tables
  
  23
- Part II
  
  51
  - Clocks and Power Interface
    
    51
    
    Clock Interface Signals
    51
    
    Overview
    51
    
    Signals
    51
    
    Power Manager Interface Control Signals
    52
    
    Nvdd_Fault
    53
    
    Block Diagram
    54
    
    Nbatt_Fault
    54
    
    Clock Interface
    56
    
    Layout Notes
    56
    
    Modes of Operations
    56
    
    Using an External 32.768-Khz Clock
    57
    
    Using the On-Chip Oscillator with a 13.000-Mhz Crystal
    57
    
    Using the On-Chip Oscillator with a 32.768-Khz Crystal
    57
    
    Power Interface
    58
    
    Power Supplies
    58
    
    Using an External 13.00-Mhz Clock
    58
  - Internal SRAM
    
    61
    
    Block Diagram
    61
    
    Overview
    61
    
    Signals
    61
    
    Layout Notes
    62
  - DMA Controller Interface
    
    63
    
    Overview
    63
    
    Signals
    63
    
    Block Diagram
    64
    
    Layout Notes
    64
    
    Fly-By DMA Transfer Signals
    65
    
    Fly-By DMA Transfers
    65
    
    Modes of Operation
    65
    
    Signals
    65
    
    Block Diagram
    66
    
    Layout Notes
    66
    
    Block Diagram
    67
    
    Flow-Through DMA Transfer Signals
    67
    
    Flow-Through DMA Transfers
    67
    
    Signals
    67
    
    Layout Notes
    68
  - System Memory Interface
    
    69
    
    Overview
    69
    
    Pxa27X Processor Memory Controller I/O Signals
    71
    
    Signals
    71
    
    Block Diagram
    73
    
    Memory Controller Layout Notes
    74
    
    Minimum and Maximum Trace Lengths for the SDRAM Signals (Excluding Sdclk<X> and SDCAS)
    74
    
    (Excludingsdclk<X> and SDCAS)
    75
    
    Minimum and Maximum Trace Lengths for the Sdclk<X> and SDCAS Signals
    75
    
    Pxa27X Processor Memory System Bus Routing Topologies
    75
    
    SDCLK and SDCAS Recommended Signal Routing Guidelines
    75
    
    Minimum Board Stack-Up Configuration Used for Signal Integrity
    76
    
    Pxa27X Processor Memory Clock and SDCAS Routing Topology
    76
    
    Modes of Operation Overview
    77
    
    SDRAM Interface
    77
    
    SDRAM Signals
    77
    
    SDRAM Memory Block Diagram
    79
    
    SDRAM Layout Notes
    80
    
    SDRAM Memory Types Supported by Pxa27X Processor
    80
    
    SA-1110 Address Compatibility Mode Memory Address Signal Mapping
    82
    
    Flash Interface Signals
    83
    
    Flash Memory Interface (Asynchronous/Synchronous)
    83
    
    Flash Memory Signals
    83
    
    Block Diagram Connecting Synchronous Flash to Ncs<1:0
    84
    
    Flash Block Diagram
    84
    
    Flash Layout Note
    84
    
    ROM Interface
    85
    
    ROM Interface Signals
    85
    
    ROM Signals
    85
    
    Block Diagram Connecting ROM to Ncs<0
    86
    
    ROM Block Diagram
    86
    
    ROM Layout Notes
    86
    
    SRAM Interface
    86
    
    SRAM Interface Signals
    87
    
    SRAM Signals
    87
    
    Block Diagram Connecting SRAM to Ncs<2
    88
    
    SRAM Block Diagram
    88
    
    SRAM Layout Notes
    88
    
    Variable Latency Input/Output (VLIO) Interface
    89
    
    VLIO Memory Interface Signals
    90
    
    VLIO Memory Signals
    90
    
    PC Card (PCMCIA) Interface
    91
    
    Variable Latency Interface Block Diagram
    91
    
    VLIO Block Diagram
    91
    
    VLIO Memory Layout Notes
    91
    
    Overview .........................................................................................................................I:
    92
    
    PC Card Interface Signals
    93
    
    PC Card Signals
    93
    
    PC-Card Block Diagrams
    94
    
    External Logic for a One-Socket Configuration Expansion PC Card
    95
    
    External Logic for a Two-Socket Configuration Expansion PC Card
    96
    
    Alternate Bus Master Interface
    97
    
    PC Card Layout Notes
    97
    
    Alternate Bus Master Interface Signals
    99
    
    Alternate Bus Master Signals
    99
    
    Alternate Bus Master Block Diagram
    100
    
    Alternate Bus Master Layout Notes
    100
    
    Alternate Bus Master Mode
    100
  - LCD Interface
    
    103
    
    Overview
    103
    
    LCD Interface Signal List
    104
    
    Signals
    104
    
    Contrast Voltage
    105
    
    Layout Notes
    105
    
    Schematics/Block Diagram
    105
    
    Backlight Inverter
    106
    
    Signal Routing and Buffering
    106
    
    Signals .........................................................................................................................II:
    106
    
    Panel Connector
    107
    
    Modes of Operation Overview
    108
    
    Passive Display Pins Required
    108
    
    Passive Monochrome Single-Scan Mode
    108
    
    Signals
    108
    
    Layout Notes
    109
    
    Passive Monochrome Single-Scan Display Typical Connection
    109
    
    Schematics/Block Diagram
    109
    
    Passive Display Pins Required
    110
    
    Passive Monochrome Single-Scan Double-Pixel Mode
    110
    
    Signals
    110
    
    Layout Notes
    111
    
    Passive Monochrome Dual-Scan Mode
    111
    
    Passive Monochrome Single-Scan Double-Pixel Data Display Typical Connection
    111
    
    Signals
    111
    
    Passive Monochrome Dual-Scan Display Typical Connection
    112
    
    Schematics / Block Diagram
    112
    
    Layout Notes
    113
    
    Passive Color Single-Scan Mode
    113
    
    Passive Display Pins Required
    113
    
    Signals
    113
    
    Layout Notes
    114
    
    Passive Color Dual-Scan Mode
    114
    
    Passive Color Single-Scan Display Typical Connection
    114
    
    Schematics/Block Diagram
    114
    
    Signals
    114
    
    Passive Display Pins Required
    115
    
    Active Color 12-Bit Per Pixel Mode
    116
    
    Passive Color Dual-Scan Display Typical Connection
    116
    
    Signals
    116
    
    LCD Interface Signal List
    117
    
    Schematics / Block Diagram
    117
    
    Active Color 12-Bit Per Pixel Display Typical Connection
    118
    
    Active Color, 16-Bit Per Pixel Mode
    118
    
    Layout Notes
    118
    
    LCD Interface Signal List
    119
    
    Schematics / Block Diagram
    119
    
    Signals
    119
    
    Active Color 16-Bit-Per-Pixel Display Typical Connection
    120
    
    Active Color, 18-Bit Per Pixel Mode
    120
    
    Layout Notes
    120
    
    LCD Interface Signal List
    121
    
    Schematics / Block Diagram
    121
    
    Signals
    121
    
    Active Color 18-Bit-Per Pixel Display Typical Connection
    122
    
    Layout Notes
    122
    
    Smart Panel
    122
    
    Schematics / Block Diagram
    123
    
    Signals
    123
    
    Layout Notes
    124
  - SSP Port Interface
    
    125
    
    Overview
    125
    
    Signals
    126
    
    SSP Serial Port I/O Signals
    126
    
    Block Diagram
    127
    
    Standard SSP Configuration Scheme
    127
    
    External Clock Source Configuration Scheme
    128
    
    External Clock Enable Configuration Scheme
    129
    
    Internal (to Pxa27X Processor) Clock Enable Configuration Design
    129
    
    Layout Notes
    130
    
    Overview
    131
    
    Signals
    131
    
    Digital-To-Analog Converter (DAC)
    132
    
    Schematic/Block Diagram
    132
    
    Other Uses of I2C
    133
    
    Layout Notes
    134
    
    Pull-Ups and Pull-Downs
    134
  - UART Interfaces
    
    135
    
    Overview
    135
    
    Signals
    136
    
    FFUART Interface Signals
    137
    
    Full Function UART
    137
    
    Full Function UART Signals
    137
    
    Types of Uarts
    137
    
    FFUART Block Diagram
    138
    
    FFUART Layout Notes
    138
    
    Bluetooth UART
    139
    
    Bluetooth UART Block Diagram
    139
    
    Bluetooth UART Signals
    139
    
    Standard UART
    140
    
    Standard UART Block Diagram
    140
    
    Standard UART Signals
    140
  - Fast Infrared Interface
    
    141
    
    Overview
    141
    
    Signals
    141
    
    Block Diagram
    142
  - USB Client Controller
    
    143
    
    Overview
    143
    
    Signals
    143
    
    Block Diagram
    144
    
    Layout Notes
    144
    
    Self-Powered Devices
    144
    
    Operation if Gpion and Gpiox Are Different Pins
    145
    
    Operation if Gpion and Gpiox Are the same Pin
    146
    
    Bus-Powered Device
    147
    
    USB On-The-GO Transceiver Usage
    148
    
    Interface to External Transceiver (OTG)
    150
    
    Interface to External Charge Pump Device (OTG)
    151
    
    Otg ID
    153
    
    Interface to External USB Transceiver (Non-OTG)
    154
    
    Overview
    157
    
    Signals
    157
    
    Block Diagram
    158
    
    Layout Notes
    159
  - I2S Interface
    
    161
    
    Overview
    161
    
    Signals
    162
    
    Block Diagram
    163
    
    Layout Notes
    163
    
    Modes of Operation Overview
    164
    
    Pxa27X Processor Provides BITCLK Signal to CODEC
    164
    
    Block Diagram
    166
    
    CODEC Provides BITCLK Signal to Pxa27X Processor
    166
  - Multimediacard/Sd/Sdio Card Controller
    
    167
    
    Layout Notes
    168
    
    MMC Protocol Signals
    170
    
    MMC/SD/SDIO Mode Using MMC Protocol
    170
    
    Modes of Operation Overview
    170
    
    MMC Protocol Block and Schematic Diagrams
    171
    
    MMC Protocol Layout Notes
    172
    
    Signals ............................................................................................II:
    172
    
    15.4.2.1 SD and SDIO Protocol Signals
    173
    
    MMC/SD/SDIO Mode Using SD or SDIO Protocols
    173
    
    SD and SDIO Protocol Block and Schematic Diagrams
    174
    
    SD and SDIO Protocol Layout Notes
    176
    
    SPI Mode Signals
    177
    
    SPI Mode with MMC, SD Card, and SDIO Card Devices
    177
    
    SPI Protocol Block and Schematic Diagrams
    178
    
    SPI Protocol Layout Notes
    178
  - Baseband Interface
    
    179
    
    Overview
    179
  - Memory Stick Host Interface
    
    181
    
    Overview
    181
    
    Schematic/Block Diagram
    181
  - Keypad Interface
    
    183
    
    Overview
    183
    
    Signals
    184
    
    Block Diagram
    185
    
    Alternate Function During Standby and Sleep Mode
    186
    
    How to Enable Specific Combinations of Direct Keys
    186
    
    Layout Notes
    186
    
    Recommended Pull-Down Resistors
    186
    
    Reduce Power During Standby and Sleep Mode
    186
    
    Using the Keypad Signals to Wake-Up from Standby and Sleep Mode
    186
    
    Interfacing to a Matrix Keypad
    187
    
    Keypad Matrix and Direct Keys and no Rotary Encoder
    188
    
    Modes of Operation Overview
    188
    
    Block Diagram
    189
    
    Keypad Matrix and Direct Keys with One Rotary Encoder
    190
    
    Block Diagram
    191
    
    Keypad Matrix and Direct Keys with Two Rotary Encoders
    192
    
    Signals
    192
    
    Block Diagram
    193
  - USIM Controller Interface
    
    195
    
    Overview
    195
    
    Pxa27X Processor USIM Interface Signals
    196
    
    Signals
    196
    
    USIM Card Interface Signals
    197
    
    Block Diagram
    198
    
    Layout Notes
    199
  - Universal Serial Bus Host Interface
    
    201
    
    Overview
    201
    
    Signals
    201
    
    Block Diagram for USB Host Differential Connection (Port 1 or Port 2)
    202
    
    Block Diagrams
    202
    
    Block Diagrams for USB Host Port 2 (Differential or Single-Ended)
    203
    
    Block Diagram for USB Host Single-Ended Connection (Port 3)
    204
    
    Layout Notes
    205
  - Real Time Clock Interface
    
    207
    
    Overview
    207
    
    Signals
    207
    
    Block Diagram
    208
    
    Layout Notes
    208
  - OS Timer Interface
    
    209
    
    Overview
    209
    
    Channel Access/Control Block
    210
    
    Pxa25X Compatibility Channels 0-3 Block
    210
    
    Signals ............................................................................................II:
    210
    
    Channels 4 - 11 Blocks
    211
    
    Layout Notes
    211
    
    Output Control
    211
  - Pulse-Width Modulator Interface
    
    213
    
    Overview
    213
    
    Signals
    213
    
    Block Diagram
    214
    
    Layout Notes
    214
  - General Purpose Input/Output Interfaces
    
    215
    
    Overview
    215
    
    Signals
    215
    
    Block Diagram/Schematic
    217
    
    Layout Notes
    217
  - Interrupt Interface
    
    219
    
    Overview
    219
    
    Signals
    220
    
    Block Diagram
    221
    
    Layout Notes
    222
  - JTAG Debug
    
    223
    
    Overview
    223
    
    Features
    224
    
    Operation
    225
    
    Signal Descriptions
    225
    
    TAP Controller Reset
    225
    
    Pull-Up Resistors
    226
    
    JTAG Instruction Register and Instruction Set
    227
    
    Bypass Register
    229
    
    Test Data Registers
    229
    
    Boundary-Scan Register
    230
    
    Data-Specific Registers
    231
    
    Flash Data Register
    231
    
    Intel Xscale ® Data Registers
    231
    
    Test Access Port (TAP) Controller
    232
    
    Capture-DR State
    233
    
    Run-Test/Idle State
    233
    
    Select-DR-Scan State
    233
    
    Shift-DR State
    233
    
    Test-Logic-Reset State
    233
    
    Exit1-DR State
    234
    
    Exit2-DR State
    234
    
    Pause-DR State
    234
    
    Update-DR State
    234
    
    Capture-IR State
    235
    
    Exit1-IR State
    235
    
    Pause-IR State
    235
    
    Select-IR-Scan State
    235
    
    Shift-IR State
    235
    
    Exit2-IR State
    236
    
    Update-IR State
    236
    
    JTAG Device Identification (ID) Register
    237
    
    Register Descriptions
    237
    
    Debug Registers
    238
    
    JTAG Test Data Registers
    238
    
    Test Register Summary
    238
  - Intel® Quick Capture Technology
    
    239
    
    Overview
    239
    
    Feature List
    240
    
    Signals
    240
    
    Block Diagram
    241
  - Appendix
    
    243
  - Pxa27X DVK Block Diagram
    
    243
  - Pxa27X Processor Developer's Kit (DVK)
    
    251
  - Pxa27X DVK Bill-Of-Materials
    
    253
  - Intel Pxa27X Processor and Intel Pxa25X Processor Differences
    
    255
  - Companion Components for Pxa27X Processor
    
    271
  - Glossary
    
    277
  - Index
    
    293
    
    Bypass Register..............................................................................II:
    293
    
    Overview......................................................................................................................II:
    295
    
    Signals .........................................................................................................................II:
    296
    
    Signals ............................................................................................II:
    297

Intel PXA27 Series Quick Start Manual (16 pages)

Processor Developer's Kit

Brand: Intel | Category: Computer Hardware | Size: 0.5 MB

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Intel PXA27 Series Manuals

Intel PXA27 Series Design Manual (298 pages)

Table of Contents

Table of Contents

Table of Contents

Part I

PCB Design Guidelines

Design Check List

Mixed Voltage Design Considerations

Power Measurements

Introduction to Part II

Package and Pins

Tables

Part II

Clocks and Power Interface

Internal SRAM

DMA Controller Interface

System Memory Interface

LCD Interface

SSP Port Interface

UART Interfaces

Fast Infrared Interface

USB Client Controller

I2S Interface

Multimediacard/Sd/Sdio Card Controller

Baseband Interface

Memory Stick Host Interface

Keypad Interface

USIM Controller Interface

Universal Serial Bus Host Interface

Real Time Clock Interface

OS Timer Interface

Pulse-Width Modulator Interface

General Purpose Input/Output Interfaces

Interrupt Interface

JTAG Debug

Intel® Quick Capture Technology

Appendix

Pxa27X DVK Block Diagram

Pxa27X Processor Developer's Kit (DVK)

Pxa27X DVK Bill-Of-Materials

Intel Pxa27X Processor and Intel Pxa25X Processor Differences

Companion Components for Pxa27X Processor

Glossary

Index

Intel PXA27 Series Quick Start Manual (16 pages)

Table of Contents

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