Common Clock (Cc) Agtl+ Signals; Figure 8. Ss Topology For Address And Data; Table 4. Processor System Bus Control Signal Routing Guidelines - Intel 852GME Design Manual

R

Figure 8. SS Topology for Address and Data

Processor
4.3.6.

Common Clock (CC) AGTL+ Signals

Table 4. Processor System Bus Control Signal Routing Guidelines

Signal Names
CPU
RESET#
BR0#
BNR#
REQ[4:0]# HREQ[4:0]#
BPRI#
DEFER#
LOCK#
TRDY#
DRDY#
ADS#
DBSY#
HIT#
HITM#
RS[2:0]#
Trace width of 4.5 mils and trace spacing of 11.5 mils within signal groups. Entire trace for each signal routed
NOTE:
on one layer (recommended) RESET# and BR0# are CC AGTL+ signals without ODT (On die termination).
For these signals Rtt should be placed near CPU: L2<= 0.5 inches. Rtt = 51.1 ±1%. Routing these signals to
4.0 inches ± 0.5 inches should maximize the setup and hold margin parameters while adhering to expected
mobile solution design constraints.
46
Vtt
Pin
Pad
Topology
GMCH
CPURST# Stripline
BREQ0# Stripline
BNR# Stripline
Stripline
BPRI# Stripline
DEFER# Stripline
HLOCK# Stripline
HTRDY# Stripline
DRDY# Stripline
ADS# Stripline
DBSY# Stripline
HIT# Stripline
HITM# Stripline
RS[2:0]# Stripline
® ®
Intel 852GME, Intel 852GMV and Intel
Pin
L1
Routing Trace Length
(Pin-to-Pin)
Nominal Impedance
Max Min
(inches) (inches)
6.0 2.0
6.0 2.0
6.0 2.0
6.0 2.0
6.0 2.0
6.0 2.0
6.0 2.0
6.0 2.0
6.0 2.0
6.0 2.0
6.0 2.0
6.0 2.0
6.0 2.0
6.0 2.0
®
852PM Chipset Platforms Design Guide
FSB Design Guidelines
Vtt Chip Set
Pad
Width & spacing
(ohms) (mils)
53 ± 15% 4.5 & 11.5
53 ± 15% 4.5 & 11.5
53 ± 15% 4.5 & 11.5
53 ± 15% 4.5 & 11.5
53 ± 15% 4.5 & 11.5
53 ± 15% 4.5 & 11.5
53 ± 15% 4.5 & 11.5
53 ± 15% 4.5 & 11.5
53 ± 15% 4.5 & 11.5
53 ± 15% 4.5 & 11.5
53 ± 15% 4.5 & 11.5
53 ± 15% 4.5 & 11.5
53 ± 15% 4.5 & 11.5
53 ± 15% 4.5 & 11.5