Routing Guidelines For Asynchronous Gtl+ And Other Signals; Table 13. Miscellaneous Signals (Signals That Are Not Data, Address, Or Strobe) - Intel Pentium 4 Design Manual

R
5.4 Routing Guidelines for Asynchronous GTL+ and
Other Signals
This section describes layout recommendations for signals other than data, strobe and address.
Table 13 lists the signals covered in this section.

Table 13. Miscellaneous Signals (Signals That Are Not Data, Address, or Strobe)

Signal Name
A20M#
BR0#
COMP[1:0]
FERR#
IGNNE#
INIT#
LINT0/INTR
LINT1/NMI
PROCHOT#
PWRGOOD
RESET#
SLP#
SMI#
STPCLK#
THERMTRIP#
VCCA
VCCIOPLL
VCC_SENSE
VID[4:0]
VSSA
VSS_SENSE
NOTES:
1. For more information on these signals, refer to Chapter 11.
2. All miscellaneous signals that require a pull up should be pulled up to VCC_CPU.
All signals must meet the AC and DC specifications as documented in the processor datasheet.
® ®
Intel Pentium 4 Processor / Intel
Type Direction
Asynchronous GTL+
AGTL+ I/O
analog
Asynchronous GTL+
Asynchronous GTL+
Asynchronous GTL+
Asynchronous GTL+
Asynchronous GTL+
OD
Asynchronous GTL+
OD
AGTL+ OD
Asynchronous GTL+
Asynchronous GTL+
Asynchronous GTL+
Asynchronous GTL+
power
power
other
other
power
other
®
850 Chipset Family Platform Design Guide
Topology Driven by
I 2 ICH2
4 Processor
I 5 External
logic
O 1a Processor
I 2 ICH2
I 2a ICH2
I 2 ICH2
O 1b Processor
I 2-b ICH2
I 4 MCH
I 2 ICH2
I 2 ICH2
I 2 ICH2
O 1b Processor
I 3 External
logic
I 3 External
logic
O Processor
O Processor
I 3 Ground
O Processor
System Bus Routing
1,3
Received Notes
by
Processor
2
Processor
ICH2 2
Processor
Processor 2
/FWH
Processor
External 2
logic
Processor 2
Processor 2
Processor
Processor
Processor
External 2
logic
Processor
Processor
V
REG
Processor
71