Intel Pentium Pro Family Manuals

Manuals and User Guides for Intel Pentium Pro Family. We have 1 Intel Pentium Pro Family manual available for free PDF download: Developer's Manual

Intel Pentium Pro Family Developer's Manual

Intel Pentium Pro Family Developer's Manual (328 pages)

Brand: Intel | Category: Computer Hardware | Size: 3.98 MB

Table of Contents

Table of Contents
3
Chapter 1 Component Introduction

17
- APIC and Bus Controller
  18
- Figure 1-1. the Pentium ® Pro Processor Integrating the CPU, L2 Cache
  18
- Bus Features
  19
- Bus Description
  20
- System Design Aspects
  21
- Efficient Bus Utilization
  21
- Multiprocessor Ready
  21
- Data Integrity
  22
- System Overview
  22
- Terminology Clarification
  23
- Compatibility Note
  25
Chapter 2 Pentium ® Pro Processor Architecture Overview

26
Chapter 3 Bus Overview

36
Chapter 4 Bus Protocol

62
Chapter 5 Bus Transactions and Operations

105
- Bus Transactions Supported
  106
- Bus Transaction Description
  107
- Memory Transactions
  107
- Figure 5-1. Bus Transactions
  107
- Memory Read Transactions
  110
- Memory Write Transactions
  110
- Memory (Read) Invalidate Transactions
  110
- Reserved Memory Write Transaction
  111
- I/O Transactions
  111
- Request Initiator Responsibilities
  112
- Addressed Agent Responsibilities
  112
- Non-Memory Central Transactions
  112
- Request Initiator Responsibilities
  113
- Central Agent Responsibilities
  113
- Observing Agent Responsibilities
  113
- Interrupt Acknowledge Transaction
  113
- Branch Trace Message
  114
- Special Transactions
  114
- Shutdown
  115
- Flush
  115
- Halt
  115
- Sync
  116
- Flush Acknowledge
  116
- Stop Grant Acknowledge
  116
- SMI Acknowledge
  116
- Deferred Reply Transaction
  117
- Request Initiator Responsibilities (Deferring Agent)
  117
- Addressed Agent Responsibilities (Original Requestor)
  118
- Reserved Transactions
  118
- Bus Operations
  118
- Implicit Writeback Response
  118
- Memory Agent Responsibilities
  119
- Requesting Agent Responsibilities
  119
- Transferring Snoop Responsibility
  120
- Figure 5-2. Response Responsibility Pickup Effect on an Outstanding Invalidation
  120
- Deferred Operations
  121
- Response Agent Responsibilities
  122
- Requesting Agent Responsibilities
  123
- Figure 5-3. Deferred Response Followed by a Deferred Reply to a Read Operation
  123
- Locked Operations
  124
- Split] Bus Lock
  125
Chapter 6 Range Registers

126
- Introduction
  127
- Range Registers and Pentium
  127
- Pro Processor Instruction
  127
- Execution
  127
  - Pro Processor
    127
- Memory Type Descriptions
  129
- UC Memory Type
  129
- WC Memory Type
  129
- WT Memory Type
  129
- WP Memory Type
  130
- WB Memory Type
  130
Chapter 7 Cache Protocol

131
- Line States
  132
- Memory Types, and Transactions
  133
- Memory Types: WB, WT, WP, and UC
  133
- Bus Operations
  133
- Naming Convention for Transactions
  134
Chapter 8 Data Integrity

135
- Error Classification
  137
- Pentium ® Pro Processor Bus Data Integrity Architecture
  137
- Bus Signals Protected Directly
  137
- Data Integrity 8.1. Error Classification
  137
- Table 8-1. Direct Bus Signal Protection
  138
- Bus Signals Protected Indirectly
  139
- Unprotected Bus Signals
  141
- Time-Out Errors
  141
- Hard-Error Response
  142
- Bus Error Codes
  142
- Parity Algorithm
  142
- Pentium Pro Processor Bus Ecc Algorithm
  142
- Error Reporting Mechanism
  142
- MCA Hardware Log
  142
- MCA Software Log
  142
- IERR# Signal
  143
- BERR# Signal and Protocol
  143
- Figure 8-1. BERR# Protocol Mechanism
  143
- BINIT# Signal and Protocol
  144
- Figure 8-2. BINIT# Protocol Mechanism
  145
- Speculative Errors
  146
- Fatal Errors
  146
- Figure 8-3. Pentium Pro Processor Errors
  146
- Pentium Pro Processor Time-Out Counter
  147
Chapter 9 Configuration

148
Chapter 10 Pentium ® Pro Processor Test Access Port (Tap)

161
- Figure 10-1. Simplified Block Diagram of Pentium
  162
- Interface
  163
- Accessing the Tap Logic
  163
- Figure 10-2. TAP Controller Finite State Machine
  163
- 10.2.1. Accessing the Instruction Register
  165
- Figure 10-4. Operation of the Pentium
  166
- 10.2.2. Accessing the Data Registers
  167
- Instruction Set
  167
- Data Register Summary
  169
- 10.4.1. Bypass Register
  169
- 10.4.2. Device ID Register
  169
- Table 10-2. TAP Data Registers
  169
- 10.4.3. bist Result Boundary Scan Register
  170
- 10.4.4. Boundary Scan Register
  170
- Reset Behavior
  170
- Table 10-3. Device ID Register
  170
- Table 10-4. TAP Reset Actions
  171
Chapter 11 Electrical Specifications

172
Chapter 12 Gtl+ Interface Specification

201
Chapter 13 Tolerant Signal Quality Specifications

229
Chapter 14 Thermal Specifications

233
Chapter 15 Mechanical Specifications

239
Chapter 16 To O Ls

253
Chapter 17 Overdrive ® Processor Socket Specification

264
Appendix Asignals Reference

291
- Alphabetical Signals Reference
  291
- A[35:3]# (I/O
  291
- A20M# (I
  292
- Ads# (I/O
  292
- A.1.2. A20M# (I)
  292
- Aerr# (I/O
  293
  - A.1.4. Aerr# (I/O)
    293
  - A.1.5. Ap[1:0]# (I/O)
    294
  - Table A-1. ASZ[1:0]# Signal Decode
    294
  - A.1.8. Bclk (I)
    295
  - Table A-2. ATTR[7:0]# Field Descriptions
    295
    
    A.1.10. Berr# (I/O)
    296
    
    A.1.12. Bnr# (I/O)
    297
    
    A.1.15. Bpri# (I)
    298
  - Table A-4. BR0#(I/O), BR1#, BR2#, BR3# Signals Rotating Interconnect
    298
  - A.1.17. Breq[3:0]# (I/O)
    299
  - Table A-5. BR[3:0]# Signal Agent Ids
    299
    
    A.1.18. D[63:0]# (I/O)
    300
    
    A.1.21. Den# (I/0)
    301
    
    A.1.24. Drdy# (I/O)
    302
  - Table A-6. DID[7:0]# Encoding
    302
  - A.1.26. Exf[4:0]# (I/O)
    303
  - Table A-7. EFX[4:0]# Signal Definitions
    303
    
    A.1.29. Frcerr(I/O)
    304
    
    A.1.31. Ierr# (O)
    305
    
    A.1.34. Intr (I)
    306
  - Table A-8. LEN[1:0]# Signals Data Transfer Lengths
    306
    
    A.1.37. Lock# (I/O)
    307
    
    A.1.41. Pwr_Gd (I)
    308
  - Table A-9. Transaction Types Defined by Reqa#/Reqb# Signals
    308
    
    A.1.43. Reset# (I)
    309
    
    A.1.45. Rs[2:0]#(I)
    310
  - Table A-10. Transaction Response Encodings
    310
    
    A.1.46. Rsp# (I)
    311
    
    A.1.49. Splck# (I/O)
    312
    
    A.1.55. Trdy# (I)
    313
    
    A.2. Signal Summaries
    314
  - Table A-12. Input Signals
    315
  - Table A-13. Input/Output Signals (Single Driver
    315
  - Table A-14. Input/Output Signals (Multiple Driver)
    317
  - Intel Literature Centers
    319

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