Table of Contents
Advertisement
EXTERNAL BUS
•
A load request has been issued to the BCU. This behavior promotes performance by
supporting early data loading.
•
A special operation is underway that requires emptying the bus queue. Examples of such
operations are execution of the HALT instruction and register stores that control logical or
physical memory configuration.
The processor can assert BSTAT on any rising CLKIN edge. Although BSTAT activation
suggests bus starvation, it does not necessarily imply that the processor definitely stall or that it is
currently stalled.
When the 80960Jx is the primary bus master and asserts BSTAT, arbitration logic can work more
intelligently to anticipate and prevent processor bus stalls. Depending on the importance of the
alternate bus master's task, ownership of the bus can be modulated. If the bus is in hold, control
can be relinquished back to the microprocessor immediately or after an optimal delay. Of course,
BSTAT can be ignored completely if the loss in processor bandwidth can be tolerated.
When the 80960Jx is not the primary bus master, the BSTAT signal becomes the means to request
the bus from the primary master. As described above, BSTAT will be activated for all loads and
fetches, but store requests do not activate BSTAT unless they fill the bus queue. If the processor
needs priority access to the bus to perform store operations, replace store instructions with the
atomic modify (
) instruction, using a mask operand of all one's.
atmod
read-modify-write instruction, so the processor will assert BSTAT when the load transaction is
posted to the bus queue. When the load begins, LOCK# is asserted, which blocks recognition of
hold requests until the store portion of
14.3
BUS APPLICATIONS
The i960Jx microprocessor is a cost-effective building block for a wide spectrum of embedded systems.
This section describes common interfaces for the 80960Jx to external memory and I/O devices.
14.3.1
System Block Diagrams
Block diagrams in
Figure 14-19
topologies representative of a number of potential 80960Jx systems. These diagrams do not
represent any particular i960Jx processor- based applications.
In most i960Jx processor systems, the 80960Jx is the primary master of the local bus. A number of
memory and I/O devices typically interface to the processor, either directly or through buffers and
transceivers. An example of such a system might be a laser beam printer.
14-34
atmod
completes.
through
Figure 14-21
are generalized diagrams with bus
is a
atmod
Advertisement
Table of Contents
