User Manuals: Intel 80386 32-bit Microprocessor

Manuals and User Guides for Intel 80386 32-bit Microprocessor. We have 2 Intel 80386 32-bit Microprocessor manuals available for free PDF download: Hardware Reference Manual, Reference Manual

Intel 80386 Reference Manual

Intel 80386 Reference Manual (291 pages)

Brand: Intel | Category: Computer Hardware | Size: 13 MB

Table of Contents

Table of Contents
8
Table of Contents
13
Figure Title Page
14
Refresh Interval Counter PAL
15
Refresh Address Counter PAL
15
- Tables
  16
- Customer Support
  17
- System Overview
  18
- Microprocessor
  20
- 80386 System Components
  20
- 80386 System Block Diagram
  21
- Corprocessors
  22
- DMA Controller
  23
- Interrupt Controller
  23
- Clock Generator
  23
- Internal Architecture
  24
Instruction Pipelining
26
80386 Functional Units
27
- Code Prefetch Unit
  28
- Execution Unit
  28
- Segmentation Unit
  29
- Paging Unit
  29
- Local Bus Interface
  30
- Bus Operations
  33
- Summary of 80386 Signal Pins
  34
- Bus Cycle Definitions
  35
- Bus States
  35
- 32-Bit Data Bus Transfers and Operand Alignment
  36
Clk2 and Clk Relationship
36
Pipelined Address Cycles
36
80386 Bus States Timing Example
37
Bus State Diagram (Does Not Include Address Pipelining)
38
Non-Pipelined Address and Pipelined Address Differences
39
Consecutive Bytes in Hardware Implementation
40
Address, Data Bus, and Byte Enables for 32-Bit Bus
40
- Possible Data Transfers on 32·Bit Bus
  41
- Read Cycle
  41
- Misaligned Transfer
  42
Non-Pipelined Address Read Cycles
43
- Misaligned Data Transfers on 32-Bit Bus
  44
- Write Cycle
  44
- Pipelined Address Cycle
  45
Non-Pipelined Address Write Cycles
46
Interrupt Acknowledge Cycle
48
Interrupt Acknowledge Bus Cycles
49
- B516 Cycle
  50
- 16-Bit Byte Enables and Operand Alignment
  51
Internal NA# and BS16# Logic
51
32-Bit and 16-Bit Bus Cycle Timing
52
Bus Timing
53

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Intel 80386 Hardware Reference Manual

Intel 80386 Hardware Reference Manual (308 pages)

Brand: Intel | Category: Processor | Size: 13 MB

Table of Contents

Table of Contents
14
Appendix A
15
Appendix B
15
Appendix C
15
Figure Title Page
15
Instruction Pipelining
29
Pipelined Address Cycles
39
Consecutive Bytes in Hardware Implementation
43
Misaligned Transfer
45
Non-Pipelined Address Read Cycles
46
Interrupt Acknowledge Bus Cycles
70

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