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®
The i960
Jx microprocessor provides a new set of essential enhancements for an emerging class
of high-performance embedded applications. Based on the i960 core architecture, it is
implemented in a proven 0.6 micron, three-layer metal process.
processor's most notable features, each of which is described in subsections that follow the figure.
These features include:
•
instruction cache
•
on-chip data RAM
•
timer units
CLKIN
PLL, Clocks,
Power Mgmt
TAP
Boundary Scan
Controller
5
7-Set
Local Register Cache
128
Global / Local
Register File
SRC1
SRC2 DEST
Three Independent 32-Bit SRC1, SRC2, and DEST Buses
Figure 1-1. i960
•
data cache
•
local register cache
•
memory-mapped control registers •
Instruction Cache
80960JT: 16 Kbyte
80960JF, JD:
4 Kbyte
80960JA:
2 Kbyte
Two-way Set Associative
Instruction Sequencer
Constants
Control
Execution
Memory
and
Interface
Multiply
Address
Divide
Generation
Unit
Unit
32-bit Addr
effective
32-bit Data
address
®
Jx Microprocessor Functional Block Diagram
CHAPTER 1
INTRODUCTION
Figure 1-1
•
bus controller unit
•
interrupt controller
external bus
Physical Region
32-bit buses
Configuration
address / data
Bus
Control Unit
Bus Request
Queues
Two 32-Bit
Timers
Programmable
Interrupt Controller
Memory Mapped
Unit
Register Interface
1 K byte
Data RAM
Direct Mapped
Data Cache
JT: 4 Kbyte
JF, JD: 2 Kbyte
JA: 1 Kbyte
1
identifies the
Control
21
Address/
Data Bus
32
Interrupt
Port
9
1-3
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