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6.2.9
bal, balx
Mnemonic:
bal
balx
Format:
bal
balx
Stores address of instruction following
Description:
to the instruction specified with the targ operand.
The
bal
do not call other procedures). The IP saved in the register provides a return IP
that the leaf procedure can branch to (using a
return from the procedure. Note that these instructions do not use the
processor's call-and-return mechanism, so the calling procedure shares its
local-register set with the called (leaf) procedure.
With
bal
value can be no farther than -2
the Intel i960 processor assembler, targ must be a label which specifies the
target instruction's IP.
performs same operation as
balx
in dst (allowing the return IP to be stored in any available register). With
the full address space can be accessed. Here, the target operand is an effective
address, which allows full range of addressing modes to be used to specify
target IP. "IP + displacement" addressing mode allows instruction to be
IP-relative. Indirect branching can be performed by placing target address in a
register and then using a register-indirect addressing mode.
See
section 2.3, "MEMORY ADDRESSING MODES" (pg. 2-6)
complete discussion of addressing modes available with memory-type
operands.
Action:
bal:
g14 = IP + 4;
temp[31:2] = sign_extension(targ[23:2]);
IP[31:2] = IP[31:2] + temp[31:2];
IP[1:0] = 0;
balx:
dst = IP + instruction_length;
# Instruction_length = 4 or 8 depending on the addressing mode used.
IP[31:2] = effective_address(targ[31:2]);
IP[1:0] = 0;
Branch and Link
Branch and Link Extended
targ
disp
targ,
dst
mem
reg
and
instructions are used to call leaf procedures (procedures that
balx
, address of next instruction is stored in register g14. targ operand
23
to (2
bal
INSTRUCTION SET REFERENCE
or
in a register then branches
bal
balx
bx
instruction) to perform a
23
- 4) bytes from current IP. When using
except next instruction address is stored
# Resume execution at new IP.
6
,
balx
for a
6-17
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