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PROGRAMMING ENVIRONMENT
3.3
MEMORY-MAPPED CONTROL REGISTERS
The i960 Jx processor gives software the interface to easily read and modify internal control
registers. Each of these registers is accessed as a 32-bit memory-mapped register (MMR) with a
unique memory address. The processor ensures that accesses to MMRs do not generate external
bus cycles.
3.3.1
Memory-Mapped Registers (MMR)
Portions of the i960 Jx processor address space (addresses FF00 0000H through FFFF FFFFH) are
reserved for memory-mapped registers (see
Space" (pg.
12-9). These memory-mapped registers (MMRs) are accessed through word-operand
memory instructions (
and
ld
and
sysctl
). Accesses to the MMRs do not generate external bus cycles. The latency in accessing
each of these registers is one cycle for
Each register has an associated access mode (user and supervisor modes) and access type (read
and write accesses).
Table 3-4
application modes of access.
The registers are partitioned into user and supervisor spaces based on their addresses. Addresses
FF00 0000H through FF00 7FFFH are allocated to user space memory-mapped registers;
Addresses FF00 8000H to FFFF FFFFH are allocated to supervisor space registers.
3.3.1.1
Restrictions on Instructions that Access Memory-Mapped Registers
The majority of memory-mapped registers can be accessed by both load (
tions. However some registers have restrictions on the types of access they allow. To ensure correct
operation, the access type restrictions for each register should be followed. The access type
columns of
Table 3-4
and
Table 3-5
Unless otherwise indicated by its access type, the modification of a memory-mapped register by a
st
instruction takes effect completely before the next instruction starts execution.
Some operations require an atomic-read-modify-write sequence to a register, most notably IPND
and IMSK. The
and
atmod
IPND and IMSK registers in an atomic manner on the i960 Jx processor. Do not use these
instruction on any other memory-mapped registers.
The
instruction can also modify the contents of a memory-mapped register atomically; in
sysctl
addition,
is the only method to read the breakpoint registers on the i960 Jx processor; the
sysctl
breakpoints cannot be read using a
3-6
section 12.3, "Architecturally Reserved Memory
instructions) and some register class instructions (
st
and
and multiple cycles for others.
ld
st
and
Table 3-5
show all the memory-mapped registers and the
indicate the allowed access types for each register.
instructions provide a special mechanism to quickly modify the
atadd
instruction.
ld
,
atmod
atadd
) and store (
) instruc-
ld
st
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