Figure 14-11. Burst Read/Write Transactions With 1,0 Wait States - Extra Tr State On Read, 16-Bit Bus - Intel i960 Jx Developer's Manual

EXTERNAL BUS
Ta
CLKIN
AD31:0
ALE
ADS
A3:2
BE1/A1
BE3/BHE
BE0/BLE
WIDTH1:0
D/C
W/R
BLAST
DT/R
DEN
RDYRCV
Figure 14-11. Burst Read/Write Transactions with 1,0 Wait States - Extra Tr State on Read,
14-20
Tw Td Td Tr Tr
D D
ADDR
In
In
00,01,10, or 11
0 1
01
16-Bit Bus
Ta Tw Td Td Tr
DATA DATA
ADDR
Out Out
00,01,10, or 11
1
0
01
F_XL034A