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INTRODUCTION
1.1
PRODUCT FEATURES
The i960 Jx processor brings many enhancements to the i960 microprocessor family, including:
•
Improvements to the core architecture
•
Low power mode
•
New instructions
•
Improved cache design
•
Enhanced bus control unit
•
Improved interrupt performance
•
JTAG testability
1.1.1
Instruction Cache
The i960 JT processor features a 16 Kbyte two-way set-associative instruction cache. The i960 JF
and JD processors employ a 4-Kbyte, two-way set-associative instruction cache. i960 JA processors
feature a 2-Kbyte instruction cache. A mechanism is provided that allows software to lock critical
code within each "way" of the cache. The cache can be disabled and is managed by use of the
and
instructions, as described in
sysctl
1.1.2
Data Cache
The i960 JT processor features a 4 Kbyte direct-mapped data cache. The i960 JF and JD
processors feature a 2-Kbyte, direct-mapped data cache that is write-through and write-allocate.
i960 JA processors feature a 1-Kbyte direct-mapped data cache. These processors have a line size
of four words and implement a "natural" fill policy. Each line in the cache has a valid bit; to
reduce fetch latency on cache misses, each word within a line also has a valid bit. See
"DATA CACHE" (pg. 4-6)
The data cache is managed through the
1.1.3
On-chip (Internal) Data RAM
The processor's 1 Kbyte internal data RAM is accessible to software with an access time of
1 cycle per word. This RAM is mapped to the physical address range of 0 to 3FFH. The first
64 bytes are reserved for the caching of dedicated-mode interrupt vectors; this reduces interrupt
latency for these interrupts. In addition, write-protection for the first 64 bytes is provided to guard
against the effects of using null pointers in 'C' and to protect the cached interrupt vectors.
1-4
section 4.4, "INSTRUCTION CACHE" (pg.
for details.
instruction; see
dcctl
4-4).
section 4.5,
section 6.2.23, "dcctl" (pg.
icctl
6-40).
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