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case 5:
Action:
case 6:
default:
}
order_wrt(subsequent_operations);
Faults:
STANDARD
Example:
ldconst 0x100,r6
sysctl r6,r7,r8
ldconst 0x204, g0
ldconst 0x20000000,g2
sysctl g0,g2,g2
Opcode:
sysctl
See Also:
dcctl, icctl
Notes:
This instruction is implemented on 80960Rx, Hx, Jx and Cx processors, and
may or may not be implemented on future i960 processors.
INSTRUCTION SET REFERENCE
memory[control_reg_addr(i,grpoff)] = memory[i+grpoff];
}
break;
# Modify One Memory-Mapped Control Register (MMR)
# src1[31:16] has lower 2 bytes of MMR address
# src2 has value to write; dst has mask.
# After operation, dst has old value of MMR
addr = (0xff00 << 16) | (src1 >> 16);
temp = memory[addr];
memory[addr] = (src2 & dst) | (temp & ~dst);
dst = temp;
break;
# Breakpoint Resource Request
acquire_available_instr_breakpoints( );
dst[3:0] = number_of_available_instr_breakpoints;
acquire_available_data_breakpoints( );
dst[7:4] = number_of_available_data_breakpoints;
dst[31:8] = 0;
break;
# Reserved, fault occurs
generate_fault(OPERATION.INVALID_OPERAND);
break;
Refer to
# Set up message.
# Invalidate I-cache.
# r7, r8 are not used.
# Set up message type and
# cache configuration mode.
# Lock half cache.
# Starting address of code.
# Execute Load and Lock.
659H
REG
section 6.1.6, "Faults" (pg.
6
6-5).
6-117
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