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11.8.1
Setting Up the Interrupt Controller
This section provides an example of setting up the interrupt controller. The following example
describes how the interrupt controller can be dynamically configured after initialization.
Example 11-6
sets up the interrupt controller for expanded-mode operation. Initially the IMSK
register is masked to allow for setup. A value that selects expanded-mode operation is loaded into
the ICON register and the IMSK is unmasked.
Example 11-6. Programming the Interrupt Controller for Expanded Mode
# Example expanded mode setup . . .
mov
0, g0
mov
1, g1
st
g0,IMSK
st
g1,ICON
st
g1,IMSK
11.8.2
Interrupt Service Routines
An interrupt handling procedure performs a specific action that is associated with a particular
interrupt vector number. For example, one interrupt handler task might initiate a timer unit request.
The interrupt handler procedures can be located anywhere in the non-reserved address space. Since
instructions in the i960 processor architecture must be word-aligned, each procedure must begin on
a word boundary.
When an interrupt handling procedure is called, the processor allocates a new frame on the
interrupt stack and a set of local registers for the procedure. If not already in supervisor mode, the
processor always switches to supervisor mode while an interrupt is being handled. It also saves the
states of the AC and PC registers for the interrupted program.
The interrupt procedure shares the remainder of the execution environment resources (namely the
global registers and the address space) with the interrupted program. Thus, interrupt procedures
must preserve and restore the state of any resources shared with a non-cooperating program. For
example, an interrupt procedure that uses a global register that is not permanently allocated to it
should save the register's contents before using the register and restore the contents before
returning from the interrupt handler.
To reduce interrupt latency to critical interrupt routines, interrupt handlers may be locked into the
instruction cache. See
section 11.9.2.2, "Caching Interrupt Routines and Reserving Register
Frames" (pg. 11-36)
for a complete description.
# mask, IMSK MMR at 0XFF008504
# unmask expanded interrupts
INTERRUPTS
11
11-31
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