Table 11-1. Interrupt Control Registers Memory-Mapped Addresses; Memory-Mapped Control Registers - Intel i960 Jx Developer's Manual

11.7.3

Memory-Mapped Control Registers

The programmer's interface to the interrupt controller is through six memory-mapped control
registers: ICON control register, IMAP0-IMAP2 control registers, IMSK register and IPND
control register. Table 11-1

Table 11-1. Interrupt Control Registers Memory-Mapped Addresses

Register Name
IPND
IMSK
ICON
IMAP0
IMAP1
IMAP2
describes the ICU registers.
Description
Interrupt Pending Register
Interrupt Mask Register
Interrupt Control Register
Interrupt Map Register 0
Interrupt Map Register 1
Interrupt Map Register 2
INTERRUPTS
Address
FF00 8500H
FF00 8504H
FF00 8510H
FF00 8520H
FF00 8524H
FF00 8528H
11
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